一种适用于Chiplet测试的通用测试访问端口控制器电路设计  

A Universal Test Access Port Controller Circuit Design for Chiplet Testing

作　　者：蔡志匡[1,2] 周国鹏 宋健 王子轩[1,2] 郭宇锋[1,2] CAI Zhikuang;ZHOU Guopeng;SONG Jian;WANG Zixuan①②GUO Yufeng(College of Integrated Circuit Science and Engineering,Nanjing University of Posts and Telecommunications,Nanjing 210003,China;National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology,Nanjing 210003,China)

机构地区：[1]南京邮电大学集成电路科学与工程学院,南京210003 [2]射频集成与微组装技术国家地方联合工程实验室,南京210003

出　　处：《电子与信息学报》2023年第5期1593-1601,共9页Journal of Electronics & Information Technology

基　　金：国家自然科学基金(61974073)。

摘　　要：在后摩尔时代里,Chiplet是当前最火热的异构芯片集成技术,具有复杂的多芯粒堆叠结构等特点。为了解决Chiplet在不同堆叠结构中的芯粒绑定后测试问题,基于IEEE 1838标准协议,该文提出一种适用于Chiplet测试的通用测试访问端口控制器(UTAPC)电路。该电路在传统测试访问端口(TAP)控制器的基础上设计了Chiplet专用有限状态机(CDFSM),增加了Chiplet测试路径配置寄存器和Chiplet测试接口电路。在CDFSM产生的配置寄存器控制信号作用下,通过Chiplet测试路径配置寄存器输出的配置信号来控制Chiplet测试接口电路以设置Chiplet的有效测试路径,实现跨层访问芯粒。仿真结果表明,所提UTAPC电路适用于任意堆叠结构的Chiplet的可测试性设计,可以有效地选择芯粒的测试,还节省了测试端口和测试时间资源并提升了测试效率。In the post-Moore era,Chiplet is the most hottest integration technique for heterogeneous integrated circuit,which is characterized by complex multi-core stacked structures.In order to solve the post-bonding test problem of Chiplet in different stacked structures,a Universal Test Access Port Controller(UTAPC)circuit is proposed based on IEEE 1838 standard protocol.Based on the traditional Test Access Port(TAP)controller,the Chiplet Dedicated Finite State Machine(CDFSM)is designed,also the Chiplet configuration registers and Chiplet test interface circuit are added.Under the influence of the configuration registers’control signals generated by the CDFSM,the configuration signals outputted from the Chiplet configuration registers are used to control the Chiplet test interface circuit to set up the effective test path of Chiplet,which realized to access cores cross layers.The simulation results demonstrate that the proposed UTAPC circuit is suitable for the design for test of Chiplet with arbitrary stacked structures.It can not only choose to test cores flexibly,but also save the resources of test ports and test time,as well as improve the test efficiency.

关 键 词：3维集成电路 Chiplet 中介层 可测试性设计 IEEE 1838标准协议 

分 类 号：TN402[电子电信—微电子学与固体电子学]