基于CORDIC旋转器的基-3 FFT算法高效设计  

Efficient Design of Radix-3 FFT Algorithm Based on CORDIC Rotator

作　　者：周群群[1] 许思耀 姚亚峰[1] 付东兵 ZHOU Qunqun;XU Siyao;YAO Yafeng;FU Dongbing(School of Mechanical Engineering and Electronic Information,China University of Geosciences,Wuhan Hubei 430074,China;Analog IC Key Laboratory,Chongqing Acoustic-Optic-Electronic Co.,LTD.,Chongqing 400060,China)

机构地区：[1]中国地质大学机械与电子信息学院,湖北武汉430074 [2]重庆声光电有限公司模拟集成电路重点实验室,重庆400060

出　　处：《电子器件》2023年第2期342-348,共7页Chinese Journal of Electron Devices

基　　金：模拟集成电路国家重点实验室稳定支持项目(JCKY2019210C058)。

摘　　要：设计出一种可以用于FPGA高效实现的基-3 FFT算法,采用改进的三端前馈延迟转换器结构,优化了延迟和运算过程。针对蝶形运算中复数乘法器占据大量内存的问题,引入了CORDIC旋转器实现输入与旋转因子相乘的运算,可以降低乘法运算的复杂度,该CORDIC旋转器采用改进的高基CORDIC算法,解决了传统的CORDIC算法迭代次数多、延迟大的问题,从而达到高吞吐率要求。该基-3 FFT算法以寻址变序、流水处理的方式,可以满足最高运行频率为404 MHz的FFT处理要求。与基于传统复数乘法器的基-3 FFT算法相比,基于CORDIC旋转器的基-3 FFT算法使功耗平均减少了22%,使总延迟平均减少了29%。A radix-3 FFT algorithm convenient for FPGA efficient implementation is designed.It adopts the improved three-terminal feedforward delay converter structure to optimize the time delay and operation process.Aiming at the complex multiplier in butterfly op-eration occupying a lot of memory,the CORDIC rotator is introduced to realize the operation of the input being multiplied by twiddle fac-tor,thus reducing the complexity of multiplication operation.This CORDIC rotator adopts an improved high-radix CORDIC algorithm,which can reduce the iteration number and time delay of traditional CORDIC algorithm,thus achieving the high throughput requirement.Through transpose access and pipeline processing,this radix-3 FFT algorithm can meet the FFT processing requirement with the highest operation frequency of 404 MHz.Compared with the radix-3 FFT algorithm based on traditional complex multiplier,the radix-3 FFT al-gorithm based on CORDIC rotator can reduce the power consumption by 22%averagely and time delay by 29%averagely.

关 键 词：基-3 FFT算法 三端前馈延迟转换器 正则有符号数 CORDIC旋转器 FPGA实现 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构] TP342.2[自动化与计算机技术—计算机科学与技术]