敏捷设计中基于机器学习的静态时序分析方法综述  

A Survey on Machine Learning-Based Technology for Static Timing Analysis in Agile Design

作　　者：贺旭 王耀[2] 傅智勇 李暾[2] 屈婉霞[2] 万海[3] 张吉良 He Xu;Wang Yao;Fu Zhiyong;Li Tun;Qu Wanxia;Wan Hai;Zhang Jiliang(College of Computer Science and Electronic Engineering,Hunan University,Changsha 410082;College of Computer Science and Technology,National University of Defense Technology,Changsha 410073;School of Software,Tsinghua University,Beijing 100084)

机构地区：[1]湖南大学信息科学与工程学院,长沙410082 [2]国防科技大学计算机学院,长沙410073 [3]清华大学软件学院,北京100084

出　　处：《计算机辅助设计与图形学学报》2023年第4期640-652,共13页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家自然科学基金(61872136,U19A2062)。

摘　　要：随着集成电路规模越来越大,设计变得越来越复杂.为了有效地提升设计生产率,芯片敏捷设计受到越来越广泛的重视.在芯片RTL-to-GDSII设计流程中,敏捷设计方法需要广泛借助机器学习技术,寻求“无人参与”的解决方案.时序性能作为芯片的重要性能指标,需要在RTL-to-GDSII设计的各个流程中进行静态时序分析.快速、准确、可靠的时序预测,可以将Sign-Off的时序性能前馈到早期设计流程中,指导早期设计的时序优化和时序收敛,减少芯片设计的迭代次数和迭代周期.文中给出敏捷设计中时序优化的流程框架,详细地梳理了RTL-to-GDSII设计流程中基于机器学习的时序分析研究现状;并从数据准备、问题建模、实用性以及通用性等多方面,探讨了敏捷设计中基于机器学习方法进行时序预测的挑战.As integrated circuits(ICs)become larger and more complex than ever,to increase design automaticity and productivity,agile design methodology has attracted a lot of attentions.In back-end design of ICs,machine learning technology for agile design are required to build a no-human-in-the-loop RTL-to-GDSII flow.For chip design,timing performance is a critical but effort-taking task.An accurate timing predictor,which is highly correlated with Sign-Off timing,is desirable to guide the timing optimization in the early design process.In this work,we propose a feasible framework for timing optimization in agile design.We also give discussion of the prior researches of machine learning-based timing predictions in RTL to GDSII design process in detail.At last,we further summarize the challenges of timing prediction in agile design from the aspects of data preparation,problem modeling,practicality and generality.

关 键 词：敏捷设计 电子设计自动化 静态时序分析 机器学习 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术]