一种低抖动时钟稳定电路的抖动分析仿真  

Jitter analysis and simulation of a low jitter clock stabilization circuit

作　　者：胡亚群 刘威 HU Yaqun;LIU Wei(School of Physical Science and Technology,Wuhan University,Wuhan 430072,China;Hubei Luojia Laboratory,Wuhan 430072,China;Shenzhen Research Institute,Wuhan University,Shenzhen 518057,China)

机构地区：[1]武汉大学物理科学与技术学院,湖北武汉430072 [2]湖北珞珈实验室,湖北武汉430072 [3]武汉大学深圳研究院,广东深圳518057

出　　处：《电子设计工程》2023年第13期1-5,共5页Electronic Design Engineering

基　　金：科技助力经济2020重点专项(SQ2020YFF0426493);武汉市应用基础前沿项目(2019010701011386);深圳市知识创新计划基础研究项目(JCYJ20180302173424902)。

摘　　要：流水线型模数转换器(Pipeline ADC)中采样时钟的占空比和抖动(jitter)会对Pipeline ADC的有效位数以及信噪比有着显著的影响。因此,该文提出一种包含时钟缓冲器、时钟沿合成电路、RC积分检测器和可控电流源反相器的低抖动时钟占空比调整电路,并对电路抖动设计及其仿真方式做了具体阐述。该电路基于TSMC 0.18μm CMOS工艺设计,经过版图后仿真后,结果表明,该电路能将20~150 MHz频率范围内、占空比为20%~80%之间的输入时钟精确调整到50%占空比,精度在±1%,输出时钟下降沿附加抖动在150 fs以内。将其应用在16 bit、80 MHz Pipeline ADC中,ADC输入信号为200 MHz时,系统信噪比能够达到71 dB。The duty cycle and jitter of sampling clock in Pipeline ADC will have a significant impact on the effective bits and signal-to-noise ratio of Pipeline ADC.Therefore,a low jitter clock duty-cycle adjustment circuit based on clock edge synthesis technology,including clock buffer,RC integral detector and inverter with controllable current source,and expounded the circuit jitter design and simulation mode in detail is proposed.The circuit is based on TSMC 0.18μm CMOS process.After post simulation,the results show that the circuit can accurately adjust the input clock in the frequency range of 20~150 MHz and the duty cycle between 20% and 80% to 50% duty-cycle,the accuracy is ±1%,and the additional jitter of the falling edge of the output clock is within 150 fs.It is applied to 16 bit,80 MHz Pipeline ADC.When the input signal of ADC is 200 MHz,the signal-to-noise ratio of the system can reach 71 dB.

关 键 词：流水线型模数转换器 时钟占空比调整器 抖动 相位噪声 

分 类 号：TN4[电子电信—微电子学与固体电子学]