基于40 nm CMOS工艺的全数字锁相环的I^(2)C接口设计  

I^(2)C Interface Design of All-Digital Phase-Locked Loop Based on 40 nm CMOS Process

作　　者：李幸和[1] 唐路[2] 万世松 LI Xinghe;TANG Lu;WAN Shisong(China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214035,China;Engineering Research Centre of RF-ICs&RF-Systems,Ministry of Education,Southeast University,Nanjing 210096,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035 [2]东南大学射频集成电路与系统教育部工程研究中心,南京210096

出　　处：《电子与封装》2023年第6期54-60,共7页Electronics & Packaging

摘　　要：基于40 nm CMOS工艺设计了一款I2C接口模块,该模块用于全数字锁相环(ADPLL)的测试与应用场景,能够输出锁相环控制字或将控制字写入锁相环内部。按照ADPLL的功能需求将接口划分为系统模块,根据ADPLL的系统特点设计了对应的时序控制模块,实现了控制字数据的读写功能。通过Verilog HDL对系统完成行为级描述,利用脚本自动化设计,能够大幅节省设计时间,易于集成到系统中。实际测试结果表明,该I^(2)C接口模块能够对ADPLL相应控制端写入控制字,依照I2C串行总线协议与外部微控制器通信,可同时实现对ADPLL控制和监测的功能,满足测试与应用需求。An I^(2)C interface module has been designed based on the 40 nm CMOS process.The module is used in the test and application scenarios of an all-digital phase-locked loop(ADPLL),and can output or write control words to the phase-locked loop.The interface is divided into system modules according to the functional requirements of the ADPLL,and the corresponding timing control module is designed according to the characteristics of the ADPLL to realize the functions of reading and writing the control word data.The behavioral-level description of the system is completed by Verilog HDL,and the use of scripts to automate the design allows for significant design time savings and easy integration into the system.The actual test results show that the I^(2)C interface module can write control words to the corresponding control side of the ADPLL,communicate with the external microcontroller according to the I^(2)C serial bus protocol,and realize the control and monitoring functions of the ADPLL at the same time to meet the test and application requirements.

关 键 词：全数字锁相环 I^(2)C接口 Verilog HDL 

分 类 号：TN402[电子电信—微电子学与固体电子学]