复合电应力对芯片使用可靠性的影响分析  

Analysis of the Influence of Composite Electrical Stress on Chip Reliability

作　　者：刘一杉 周亮 黄炜[1] LIU Yi-san;ZHOU Liang;HANG Wei(Sichuan Institute of Solid-State Circuits,China Electronics Technology Group Corp.,Chongqing 400060)

机构地区：[1]中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《环境技术》2023年第5期55-58,共4页Environmental Technology

摘　　要：新的应用要求集成电路芯片扩展其工作领域工作在高压、高温、高频和大功率等多重复合条件下,使得集成电路面临的可靠性问题日益严峻。而芯片集成度的增加、工艺尺寸的缩小导致集成电路芯片抗环境应力能力降低。而电应力作为最直接、对器件影响最大的一种应力,其对芯片可靠性的影响最为显著,本文选取一款大规模专用集成电路芯片故障作为典型案例,分析实际应用过程中复合电应力对芯片可靠性的具体影响,为类似复合应力的影响分析提供参考。New applications require integrated circuit chips to expand their work fields and work under multiple complex conditions such as high voltage,high temperature,high frequency and high power,which makes the reliability problems faced by integrated circuits increasingly serious.However,the increase of chip integration and the reduction of process size lead to the reduction of the ability of integrated circuit chips to resist environmental stress.As the most direct stress that has the greatest impact on the device,electrical stress has the most significant impact on the chip reliability.This paper selects a large scale ASIC chip fault as a typical case to analyze the specific impact of composite electrical stress on chip reliability in the actual application process,and provides a reference for the impact analysis of similar composite stress.

关 键 词：集成电路 复合电应力 失效分析 长期可靠性 

分 类 号：TN406[电子电信—微电子学与固体电子学]