一种高电源抑制比的低压差线性稳压器设计  

Design of a Linear Low Dropout Regulator with High Power Rejection Ratio

作　　者：王永春 WANG Yongchun(Shanghai Canrui Technology Co.,Ltd.,Shanghai 200072,China)

机构地区：[1]上海灿瑞科技股份有限公司,上海200072

出　　处：《集成电路应用》2023年第5期11-13,共3页Application of IC

摘　　要：阐述一款高PSRR的LDO电路设计,给出了基本结构线性稳压器的电源抑制比计算,然后根据计算给出电路实现,探讨在高频段范围,一个电源扰动的抵消设计。这个LDO器件在5V 0.18μm CMOS工艺上实现,并且在100kHz的频率范围内实现了>60db的电源抑制比。This paper describes the design of a high PSRR LDO circuit,provides the calculation of the power suppression ratio of the basic structure linear regulator,and then provides the circuit implementation based on the calculation.It explores the design of a power disturbance cancellation in the high-frequency range.This LDO device operates at 5V 0.18μm implemented on the CMOS process,and achieved a power suppression ratio of>60db in the frequency range of 100kHz.

关 键 词：电路设计 电源抑制比 线性稳压器 环路稳定性 

分 类 号：TN402[电子电信—微电子学与固体电子学]