基于SS-LMS算法的自适应DFE均衡电路  

Self-Adaptive DFE Circuit Based on SS-LMS Algorithm

作　　者：李晓东 沈剑良[1] 李沛杰 张传波 LI Xiaodong;SHEN Jianliang;LI Peijie;ZHANG Chuanbo(Information Engineering University,Zhengzhou 450001,China)

机构地区：[1]信息工程大学,河南郑州450001

出　　处：《信息工程大学学报》2023年第3期303-309,共7页Journal of Information Engineering University

基　　金：国家科技重大专项资助项目(2016ZX01012101)。

摘　　要：针对信道传输对高速串行数据带来的码间串扰问题,提出一种基于符号最小均方根(SS-LMS)算法的半速率判决反馈均衡器(DFE)结构。基于Slicer和积分器电路的结构优化,实现面积和功耗的优化。采用28 nm CMOS工艺实现了连续时间线性均衡器(CTLE)和8抽头DFE组合结构的SerDes电路。测试结果表明,所设计的均衡电路能够将通过38 inch背板传输的16 Gbps信号的眼图水平张开度达到0.56 UI,最大功耗12.25 mW/Gbps。To address the inter-symbol interference caused by channel transmission on high-speed serial data,a half-rate decision feedback equalizer(DFE)structure based on the sign-sign least mean square(SS-LMS)algorithm is proposed.Based on the structural optimization of the slicer and integrator circuit,the optimization of area and power consumption is realized.The 28 nm CMOS process is used to realize the SerDes circuit with a combination of continuous-time linear equalizer(CTLE)and 8-tap DFE.The test results show that the designed equalization circuit can open the horizontal opening of the 16 Gbps signal transmitted through the 38 inch backplane to 0.56 UI,and the maximum power consumption is 12.25 mW/Gbps.

关 键 词：判决反馈均衡器 符号最小均方根 码间干扰 高速串行收发器 自适应均衡 

分 类 号：TN715[电子电信—电路与系统]