一种基于新型自适应校准技术的小数频率综合器的设计  

Design of a Fractional-N Frequency Synthesizer Using a Novel Adaptive Calibration Technology

作　　者：郑立博[1,2] 解昊炜 王贵宇 赵科伟 郭宇锋[1,2] 刘轶 ZHENG Libo;XIE Haowei;WANG Guiyu;ZHAO Kewei;GUO Yufeng;LIU Yi(College of Electronic and Optical Engineering,Nanjing University of Posts and Telecommunications,Nanjing 210003,P.R.China;National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology,Nanjing University of Posts and Telecommunications,Nanjing 210003,P.R.China)

机构地区：[1]南京邮电大学电子与光学工程学院,南京210003 [2]南京邮电大学射频集成与微组装国家地方联合工程实验室,南京210003

出　　处：《微电子学》2023年第2期247-254,共8页Microelectronics

基　　金：南京邮电大学引进人才科研启动基金(NY221015);江苏省研究生科研与实践创新计划项目(KYCX22_0924)。

摘　　要：基于EPC Class-1 Generation-2协议规定,对工作于全球UHF RFID频段的频率综合器的设计指标进行了分析。采用标准0.18μm CMOS工艺,集成自适应频率校准模块设计了一种新颖的低相位噪声、快速锁定的小数频率综合器。其中,LC-VCO基于无尾电流源式设计,利用二次谐波滤波技术显著降低了带内相位噪声;自适应频率校准电路则区别于传统的二进制比较法,基于新颖的逐次比较法以减小VCO的4位数控逻辑电压的比较次数,因而可以快速确定VCO的控制字并缩短锁定时间。仿真结果表明,自适应校准阶段的时间仅约6.3μs,环路整体锁定时间低于23.2μs,100 kHz频偏处的相位噪声性能为-106.3 dBc/Hz,1 MHz频偏处为-126.1 dBc/Hz,整体功耗为84 mW。与最近发布的先进的CMOS小数频率综合器的性能相比,所设计的小数频率综合器实现了更优的相位噪声性能,同时能以较短的锁定时间以及较低的功耗工作。Based on the EPC class-1 generation-2 protocol,the system specifications of the frequency synthesizer working in the global UHF RFID band was analyzed.By using the standard O.18μm CMOS process and integrating a new adaptive frequency calibration module,a low phase noise,fast locking fractional frequency synthesizer was designed.The LC-VCO was based on the tailless current source topology and utilized the second harmonic filtering technology to significantly reduce the phase noise in band.In addition,the adaptive frequency calibration circuit was different from the traditional binary comparison method.It was based on a novel successive comparison method to reduce the comparison time of the 4-bit digital logical control voltage of the VCO.Therefore,the control words of the VCO could be quickly determined and the locking time could be improved.The simulation results show that the locking time is only 6.3μs during the adaptive calibration period,the overall locking time of the loop is lower than 23.2μs,its phase noise performance is-106.3 dBc/Hz at 100 kHz frequency offset and-126.1 dBc/Hz at 1 MHz frequency offset,and the overall power consumption is 84 mW.Compared with the performance of the recently released advanced CMOS fractional-N frequency synthesizer,the proposed one achieves considerable phase noise performance,and works with shorter locking time and lower power consumption.

关 键 词：小数频率综合器 自适应校准电路 混合集成电路 

分 类 号：TN432[电子电信—微电子学与固体电子学]