基于符号补偿的RISC-V处理器乘法器优化  

Optimization of RISC-V Processor Multiplier Based on Sign Compensation

作　　者：高嘉轩 刘鸿瑾 施博 张绍林 华更新[1] GAO Jiaxuan;LIU Hongjin;SHI Bo;ZHANG Shaolin;HUA Gengxin(Beijing Institute of Control Engineering,Beijing 100190,China;Beijing Xuanyu Space Technology Co.,Ltd.,Beijing 100080,China)

机构地区：[1]北京控制工程研究所,北京100190 [2]北京轩宇空间科技有限公司,北京100080

出　　处：《计算机测量与控制》2023年第7期258-264,270,共8页Computer Measurement &Control

摘　　要：针对高性能RISC-V处理器乘法运算延迟过长的问题,改进了基本乘法器中的基4-Booth编码以及Wallace树型结构,提出了基于符号补偿的基4-Booth编码以及交替使用3-2压缩器和4-2压缩器的Wallace树型结构;基于符号补偿的基4-Booth编码减少了部分积的数量,降低了符号位进位翻转带来的功耗;改进的Wallace树型结构减少了部分积累加所花费的时钟周期,缩短了乘法器的关键路径,降低了乘法指令的执行延迟;利用VCS仿真验证了改进的乘法器功能正确性,通过板级测试评估了其性能;结果表明,文章的乘法器功能正确,相较于PicoRV32,执行整型乘法指令所花费的时钟周期缩短了88.2%。Dhrystone分数提高了71.7%,功耗降低了4.9%。For the problem of excessive latency in multiplication operations of high-performance RISC-V processors,the basic multiplier by modifying the radix-4 Booth based encoding and Wallace tree architecture are improved.A sign-compensation-based radix-4-Booth encoding method and a Wallace tree structure with alternating use of 3-2 compressors and 4-2 compressors are proposed.The radix-4 Booth based encoding with signed compensation reduces the number of partial products and decreases the power consumption caused by sign bit carry flipping.The improved Wallace tree structure reduces the clock cycles required for partial product accumulation,shortening the critical path of the multiplier and reducing the execution delay of multiplication instructions.VCS simulation is used to verify the functionality of the improved multiplier,and its performance is evaluated through the board-level testing.The results show that the proposed multiplier functions are correct.Compared to the PicoRV32,the required clock cycles for executing the integer multiplication instructions are reduced by 88.2%.The Dhrystone score increased by 71.7%,and the power consumption decreased by 4.9%.

关 键 词：RISC-V 处理器 乘法器 符号补偿 BOOTH编码 Wallace树型结构 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]