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作 者:唐俊龙[1] 卢英龙 戴超雄 邹望辉 李振涛 TANG Junlong;LU Yinglong;DAI Chaoxiong;ZOU Wanghui;LI Zhentao(School of Physical and Electronic Sciences,Changsha University of Science and Technology,Changsha 410114,China;Hunan Great-Leo Microelectronics Co.Ltd.,Changsha 410003,China)
机构地区:[1]长沙理工大学物理与电子科学学院,湖南长沙410114 [2]湖南毂梁微电子有限公司,湖南长沙410003
出 处:《湖南大学学报(自然科学版)》2023年第8期147-152,共6页Journal of Hunan University:Natural Sciences
基 金:柔性电子材料基因工程湖南省重点实验室开放基金(202015)。
摘 要:随着集成电路制造工艺的进步与芯片集成度的提升,对于低功耗芯片的需求越来越大.时钟网络功耗占芯片总功耗的40%以上,优化时钟网络的功耗已成为高性能集成电路设计中最重要的目标之一.本文提出了一种新的寄存器聚类方法来生成时钟树的叶级拓扑结构,通过限制群组的扇出、负载和范围,对寄存器进行合理分组,减少了缓冲器的插入数目和总布线长度,有效降低时钟网络功耗.将该方法整合到传统的时钟树综合(CTS)流程中,在ISCAS89基准电路上测试并分析其有效性.实验结果表明,该寄存器聚类方法在不影响时钟树最大延时的情况下,有效减少了时钟网络20%以上的功率耗散和20%以上的时钟偏移.With the advancement of integrated circuit manufacturing technology and the improvement of chip integration,the demand for low-power chips has been steadily increasing.The clock network is responsible for more than 40%of the total power consumption of the chip.Consequently,optimizing the power consumption of the clock network has become one of the most important goals in the design of high-performance integrated circuits.In this paper,a new register clustering method is proposed to generate the leaf level topology of the clock tree.By carefully limiting the fan-out,load,and range of the clusters to reasonably group the registers,the method effectively reduces the number of buffer insertions and the total wiring length,and the clock network power consumption is also significantly reduced.The method is integrated into the traditional clock tree synthesis(CTS)flow,and its effectiveness is tested and analyzed on the ISCAS89 benchmark circuit.Experimental results show that the register clustering method effectively reduces the power dissipation of the clock network by more than 20%and the clock offset by more than 20%,without affecting the maximum delay of the clock tree.
分 类 号:TN402[电子电信—微电子学与固体电子学]
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