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作 者:洪方磊 薛萌 郭汉明[1] HONG Fanglei;XUE Meng;GUO Hanming(School of Optical-Electrical and Computer Engineering,University of Shanghai for Science and Technology,Shanghai 200093,China)
机构地区:[1]上海理工大学光电信息与计算机工程学院,上海200093
出 处:《软件导刊》2023年第8期156-163,共8页Software Guide
基 金:上海市地方能力建设项目(21010502900)。
摘 要:针对激光扫描共聚焦显微镜的数据高速传输需求,设计了一种基于DDR3和千兆以太网的大数据缓存与高速传输系统。该系统以Artix-7系列的FPGA芯片XC7A35T为主控芯片,基于Verilog语言在Xilinx FPGA的开发平台Vivado上设计了整个系统的控制方案;缓存模块采用Micron公司的DDR3芯片MT41J128M16HA,结合Xilinx提供的DDR控制器IP核与FIFO,对上游的大量数据进行高速缓存;同时采用Realtek公司的以太网芯片RTL8211实现了基于UDP、IP协议的以太网帧组包与解包,通过RJ45以太网接口以1000 Mbps的速率从上位机接收指令或发送数据。测试结果表明,该方案能将数据高速存储到DDR3中,并实时高效地传输到上位机中,实时传输速率达到118.75 Mbyte/s。在工作过程中,该系统稳定性高、误码率低,且电路集成度高、控制时序精确,非常适合作为激光扫描共聚焦成像设备的数据传输系统。Aiming at the demand of high-speed data transmission for laser scanning confocal microscope,a large data caching and high-speed transmission system based on DDR3 and gigabit Ethernet is designed.The system uses Artix-7 series FPGA chip XC7A35T as the main control chip,and designs the control scheme of the whole system on Xilinx FPGA development platform Vivado with Verilog language.The cache module uses Micron's DDR3 chip MT41J128M16HA,combined with the DDR controller IP core and FIFO provided by Xilinx,to cache a large amount of upstream data.At the same time,Realtek's Ethernet chip RTL8211 is used to realize Ethernet frame grouping and unpack⁃ing based on UDP and IP protocols.It receives instructions from the host computer or sends data to the host computer at a rate of 1000 Mbps through RJ45 Ethernet interface.The test results show that the scheme can store data in DDR3 at high speed and transmit it to the host comput⁃er efficiently in real time,and the real-time transmission rate reaches 118.75 Mbyte/s.The system has high stability,low bit error rate,high circuit integration and precise control timing,which is very suitable for the data transmission system of laser scanning confocal imaging equipment.
关 键 词:共聚焦显微镜 FPGA DDR3 SDRAM 千兆以太网 VERILOG 高速缓存与传输
分 类 号:TP302.1[自动化与计算机技术—计算机系统结构]
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