8位高速低功耗流水线型ADC优化设计研究  

Research of Digital Correction Technologies for 8-bit High Speed and Low Power Pipelined ADC

作　　者：黄玮[1] 谢亚伟[1] 居水荣[1] HUANG Wei;XIE Yawei;JU Shuirong

机构地区：[1]江苏信息职业技术学院,江苏无锡214153

出　　处：《科技创新与应用》2023年第24期60-63,67,共5页Technology Innovation and Application

基　　金：江苏省教育厅高校优秀科技创新团队项目(苏教科[2021]1号)。

摘　　要：采用每级为1.5位精度的7级流水线结构,即7级子ADC设计一个8位80 MS/s的低功耗模数转换电路。通过设计精简且高效的数字校准和输出寄存模块,消除ADC实现过程中各种因素的影响,提高ADC的精度和信噪比。采用0.18μm CMOS工艺完成加工后,测得该ADC在输入信号为36.25 MHz,采样速率为80 MHz下的信噪比(SNR)为49.6 dB,有效位数(ENOB)接近8位,典型的功耗电流只有18 mA,整个ADC的芯片面积为0.5 mm^(2)。A low-power analog-to-digital conversion circuit with 8-bit 80 MS/s is designed using a 7-stage pipelined structure with 1.5-bit precision per stage,that is,7-stage sub-ADC.Through the design of a concise and efficient digital calibration and output storage module,the influence of various factors in the implementation of ADC is eliminated,and the accuracy and signal-to-noise ratio of ADC are improved.After processing with 0.18μm CMOS process,the signal-to-noise ratio(SNR)of the ADC is 49.6 dB when the input signal is 36.25 MHz and the sampling rate is 80 MHz,and the effective numbers of bits(ENOB)is close to 8 bits.The typical power consumption current is only 18 mA,and the chip area of the whole ADC is 0.5 mm^(2).

关 键 词：流水线型ADC 采样保持电路 动态比较器 数字校准和输出寄存 低功耗 信噪比 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]