一种全速率线性25Gb/s时钟数据恢复电路  

A Full-Rate Linear 25 Gbps Clock and Data Recovery Circuit

作　　者：张书豪 黄启俊[1] 常胜[1] 王豪[1] 何进[1] ZHANG Shuhao;HUANG Qijun;CHANG Sheng;WANG Hao;HE Jin(School of Physics and Technology,Wuhan University,Wuhan 430072,CHN)

机构地区：[1]武汉大学物理科学与技术学院,武汉430072

出　　处：《半导体光电》2023年第3期344-349,共6页Semiconductor Optoelectronics

基　　金：国家自然科学基金项目(61774113,61874079,62074116,81971702)。

摘　　要：面向高速光通信系统的应用,提出了一种全速率线性25 Gb/s时钟数据恢复电路(Clock and Data Recovery Circuit,CDRC)。CDRC采用了混频器型线性鉴相器和自动锁频技术来实现全速率时钟提取和数据恢复。在设计中没有使用外部参考时钟。基于45 nm CMOS工艺,该CDR电路从版图后仿真结果得到:恢复25 Gb/s数据眼图的差分电压峰峰值V_(pp)和抖动峰峰值分别为1.3 V和2.93 ps;输出25 GHz时钟的差分电压峰峰值V_(pp)和抖动峰峰值分别为1 V和2.51 ps,相位噪声为-93.6 dBc/Hz@1 MHz。该芯片面积为1.18×1.07 mm^(2),在1 V的电源电压下功耗为51.36 mW。In this paper,a full-rate linear 25 Gbps clock and data recovery circuit(CDRC) is proposed for the application of high-speed optical communication systems.To achieve full-rate clock extraction and data recovery,CDRC employed a mixer-based linear phase detector and automatic frequency locking technique.No external reference clock was used in the design.Based on a 45 nm CMOS process,the CDR circuit from the post-plate simulation results achieves that the peak-to-peak differential voltage V_(pp) and peak-to-peak jitter of the recovered 25 Gbps data eye diagram are 1.3 V and 2.93 ps,respectively.The output 25 GHz clock has a differential peak-to-peak voltage V_(pp) and peak-to-peak jitter of 1 V and 2.51 ps,respectively,with phase noise of-93.6 dBc/Hz@1 MHz.The chip has an area of 1.18×1.07 mm^(2) and consumes 51.36 mW at a supply voltage of 1 V.

关 键 词：光通信 时钟数据恢复 线性鉴相器 鉴频器 CMOS 

分 类 号：TN432[电子电信—微电子学与固体电子学]