一种快速瞬态响应的LDO设计  

Design for a Fast Transient Response LDO

作　　者：孙力 王志亮[1] 杨雨辰 谭庶欣 陈靖 Sun Li;Wang Zhiliang;Yang Yuchen;Tan Shuxin;Chen Jing(School of Information Science and Technology,Nantong University,Nantong 226000,China)

机构地区：[1]南通大学信息科学技术学院,江苏南通226000

出　　处：《半导体技术》2023年第8期690-698,共9页Semiconductor Technology

基　　金：江苏省科技成果转化专项资金项目(BA2022001);江苏省高等学校自然科学研究重大项目(22KJA510005)。

摘　　要：针对传统低压差线性稳压器(LDO)的瞬态响应差、电源抑制比(PSRR)低、片外电容大等问题,提出了一种由采样运算放大器和补偿运算放大器构成的新型摆率增强电路,改善了LDO的瞬态响应能力,实现了无片外电容设计。电路基于BCD-120 V CMOS工艺完成了建模。仿真结果显示,负载电流为50 mA时,10、103和104Hz下的PSRR分别为108、96和80 dB;负载调整率为0.002 95 V·A^(-1);典型TT工艺角25℃/5 V条件下,1μs内负载电流从100μA跳变到500 mA,输出端上冲电压为19.16 mV,响应时间为0.4μs,下冲电压为56.41 mV,响应时间为0.2μs。To solve the problems of poor transient response,low power supply rejection ratio(PSRR)and large off-chip capacitance of the traditional low dropout regulator(LDO),a new slew rate enhancement circuit composed of a sampling operational amplifier and a compensation operational amplifier was proposed,which improved the transient response of the LDO and realized off-chip capacitorless design.The circuit was modeled based on the BCD-120 V CMOS process.The simulation results show that when the load current is 50 mA,the PSRR at 10、10^(3)and 10^(4)Hz are 108,96 and 80 dB,respectively.The load adjustment rate is 0.00295 V.A-1.Under the typical TT process corner of 25℃/5 V,the load current jumps from 100μA to 500 mA within 1μs.The overshoot voltage is 19.16 mV at the output end,and the response time is 0.4μs.The undershoot voltage is 56.41 mV,and the response time is 0.2μs.

关 键 词：低压差线性稳压器(LDO) 瞬态响应 电源抑制比(PSRR) 无片外电容 摆率增强 

分 类 号：TM44[电气工程—电器] TN43[电子电信—微电子学与固体电子学]