心电信号监测轻量化残差神经网络硬件IP设计  

Hardware IP design of lightweight residual neural networks for ECG signal detection

作　　者：谢文鑫 史纪广 李宙童 黄启俊[1] XIE Wenxin;SHI Jiguang;LI Zhoutong;HUANG Qijun(School of Physics and Technology,Wuhan University,Wuhan 430072,China;Huangpu Branch of Shanghai Ninth People’s Hospital,Shanghai Jiaotong University School of Medicine,Shanghai 200011,China)

机构地区：[1]武汉大学物理科学与技术学院,湖北武汉430072 [2]上海交通大学医学院附属第九人民医院黄浦分院,上海200011

出　　处：《电子设计工程》2023年第19期15-19,24,共6页Electronic Design Engineering

基　　金：国家自然科学基金项目(81971702,61874079)。

摘　　要：针对实时心电数据的自动诊断,文中设计了一种适合硬件实现的轻量化残差神经网络结构,并将其实现为可用于便携式心电检测系统的硬件IP。通过在FPGA平台上搭建验证系统,完成了该硬件IP的部署和验证。经过实测心电数据验证,硬件IP模块可实现正常心电图(N)、房性早搏(A)、心动过速(T)、心动过缓(B)四种心电信号的自动分类。与嵌入式软件实现方式相比,硬件IP模块准确率达到99.6%,计算速度提升了2.07倍,可以满足实时性要求,特别适合应用于便携式心电检测系统。For automatic diagnosis of real-time ECG data,this paper designs a lightweight residual neural network structure suitable for hardware implementation and implements it as a hardware IP that can be used in portable ECG detection systems.The deployment and verification of this hardware IP is completed by building a verification system on an FPGA platform.After the validation of the measured ECG data,the hardware IP module can realize the automatic classification of four ECG signals:normal ECG(N),atrial premature beats(A),tachycardia(T),and bradycardia(B).Compared with the embedded software implementation method,the hardware IP module achieves 99.6%accuracy and 2.07 times higher calculation speed,which can meet the real-time requirements and is especially suitable for application in portable ECG detection systems.

关 键 词：心电信号 残差神经网络 轻量化 FPGA 

分 类 号：TN911.72[电子电信—通信与信息系统]