检索规则说明:AND代表“并且”;OR代表“或者”;NOT代表“不包含”;(注意必须大写,运算符两边需空一格)
检 索 范 例 :范例一: (K=图书馆学 OR K=情报学) AND A=范并思 范例二:J=计算机应用与软件 AND (U=C++ OR U=Basic) NOT M=Visual
作 者:杨睿[1] 夏涛 黄瑛[1] Yang Rui;Xia Tao;Huang Ying(School of Electric Power Engineering,Nanjing Institute of Technology,Nanjing 211167,China)
出 处:《机电工程技术》2023年第9期246-251,共6页Mechanical & Electrical Engineering Technology
基 金:江苏省自然科学基金青年基金项目(BK20201034)。
摘 要:针对角位置测量电路存在的计数脉冲信号处理频率较低和抗干扰性差的缺点,设计了一种以C8051F020单片机、MAX7000AE系列现场可编程门阵列(Field-Programmable Gate Array,CPLD)和MC3486差分脉冲信号处理芯片为核心元件的多通道光电编码器脉冲信号测量电路;分别设计了CPLD的四倍频、脉冲计数及判向逻辑电路和VHDL程序;通过使用高精度光电编码器,满足了在高转速条件下,大幅提升角位置测量精度,并可方便地进行多测量通道扩展的要求。对影响高频脉冲计数电路正常工作的各类外部干扰因素进行分析,使用高频脉冲进行采样比较的方法,设计了一种由检测脉冲沿得到的DIR判向信号作为D触发器的选通信号的方法,以滤除计数脉冲上的毛刺干扰信号,从而保证了单方向计数,降低了发生误计数的可能性;并通过Quartus II软件对所设计方法输出信号的时序功能进行了仿真,并验证了该电路设计方案的正确性。For the shortcomings such as receiving low frequency pulse signal and poor immunity in the angular position measuring circuit,a multi-channels photoelectric encoder signal measurement circuit which is based on C8051F020 MCU,MAX 7000AE series CPLD and MC3486 differential pulse signal processing chip is designed.The VHDL procedures and CPLD internal logic circuits for the fourfold frequency direction judgment circuit and pulse counting circuit are designed.With a high-precision photoelectric encoder,it meets the requirements of greatly improving the angular position measurement accuracy under high-speed conditions,and can easily expand multiple measurement channels.Analyze various external interference factors that affect the normal operation of the high-frequency pulse counting circuit,use high-frequency pulses for sampling and comparison,and design a DIR direction judgment signal obtained by detecting the pulse edge as the gate signal of the D flip-flop The method to filter out the burr interference signal on the counting pulse,thus ensuring one-way counting and reducing the possibility of miscounting;And by Quartus II software,the timing sequence function of the output signal of the designed method is simulated,and the correctness of the circuit design scheme is verified.
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在链接到云南高校图书馆文献保障联盟下载...
云南高校图书馆联盟文献共享服务平台 版权所有©
您的IP:216.73.216.38