基于三路同源时钟的TLK2711高速数传接口设计  

Design of TLK2711 high speed data transfer interface based on three-way homologous clock

作　　者：温超然 聂婷[1] 王晓峰[1,2] 农深恺 黄良 Wen Chaoran;Nie Ting;Wang Xiaofeng;Nong Shenkai;Huang Liang(Changchun Institute of Optics and Mechanical Sciences,Chinese Academy of Sciences,Changchun 130033,China;University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院长春光学精密机械与物理研究所,长春130033 [2]中国科学院大学,北京100049

出　　处：《电子测量技术》2023年第11期173-178,共6页Electronic Measurement Technology

基　　金：国家自然科学基金(62105328)项目资助。

摘　　要：随着卫星载荷相机的分辨率不断提升,其获取的图像数据量也迅速增加,如何将载荷数据高速且可靠地传输至后端设备处理是当前所需要解决的问题。本文在高速SERDES接口芯片TLK2711和三路同源时钟的工作原理上进行研究应用,针对星载TLK2711高速数传链路中出现的传输误码等问题做出了分析,提出了一种基于三路同源时钟的高速数传接口设计,并对该高速数传接口具体设计做了详细描述。首先分析原始方案,即无外部参考时钟的FPGA向TLK2711输出时钟信号的缺点,并在原方案基础提出改进方案,在原电路基础上加入三路同源时钟为FPGA和TLK2711提供参考时钟。深入分析了误码率产生的原因及影响,从而提出了最佳相位检测和RS编码,并对其在高速数传接口应用的可行性进行了验证。对接口设计进行验证,实验结果表明,采用TLK2711高速数传接口可实现高达2.5 Gbit/s的数据传输,相比较于原始方案,基于三路同源时钟的TLK2711高速数传接口设计数据时钟抖动下降59.5%,采用的RS编码纠错能力强,使得CRC错误数大幅度降低,显著降低了误码率,硬件实现简单,增强了接口的工作稳定性。With the increasing resolution of satellite payload cameras,the amount of image data acquired by them also increases rapidly.How to transfer payload data to the back-end device for high-speed and reliable processing is the current problem to be solved.In this paper,the high-speed SERDES interface chip named TLK271l and three-way homologous clock working principle are studied and applied,and the transmission error in the high-speed data link of the satellite TLK271l is analyzed.A high-speed data interface design based on three-way homologous clock is presented,and the specific design of the high-speed data interface is described in detail.Firstly,the disadvantage of the original scheme,that is,the output data signal to TLK2711 by the field programmer without additional reference clock,is analyzed.Based on the original scheme,an improved scheme is proposed.Three-way homologous clocks are added to the original circuit to provide reference clocks for the field programmer and TLK271l.The causes and effects of bit error rate are analyzed in depth,and the optimal phase detection and RS encoding are proposed,and the feasibility of its application in high-speed data transmission interface is verified.The interface design is validated.The experimental results show that the TLK2711 high-speed data transfer interface can achieve up to 2.5 Gbit/s data transmission.Compared with the original scheme,the data clock jitter of TLK2711 high-speed data transfer interface design based on three-way homologous clock is reduced by 59.5%,and the RS encoding error correction capability is strong,which greatly reduces the error rate of CRC,significantly reduces the error rate of hardware implementation,and enhances the working stability of the interface.

关 键 词：高速串行传输 高速数传接口 TLK2711 三路同源时钟 最佳相位检测 RS编码 

分 类 号：TP2[自动化与计算机技术—检测技术与自动化装置]