低面积与低延迟开销的三节点翻转容忍锁存器设计  

Design of a Low-area and Low-delay Triple-Node-Upset Tolerant Latch

作　　者：闫爱斌 申震 崔杰[1] 黄正峰 YAN Aibin;SHEN Zhen;CUI Jie;HUANG Zhengfeng(School of Computer Science and Technology,Anhui University,Hefei 230601,China;School of Microelectronics,Hefei University of Technology,Hefei 230601,China)

机构地区：[1]安徽大学计算机科学与技术学院,合肥230601 [2]合肥工业大学微电子学院,合肥230601

出　　处：《电子与信息学报》2023年第9期3272-3283,共12页Journal of Electronics & Information Technology

基　　金：国家自然科学基金(62274052,61974001)。

摘　　要：随着纳米级CMOS集成电路的不断发展,锁存器极易受恶劣的辐射环境影响,由此引发的多节点翻转问题越来越严重。该文提出一种基于双联互锁存储单元(DICE)和2级C单元的3节点翻转(TNU)容忍锁存器,该锁存器包括5个传输门、2个DICE和3个C单元。该锁存器具有较小的晶体管数量,大大减小了电路的硬件开销,实现低成本。每个DICE单元可用来容忍并恢复单节点翻转,而C单元具有错误拦截特性,可屏蔽由DICE单元传来的错误值。当任意3个节点翻转后,借助DICE单元和C单元,该锁存器可容忍该错误。基于集成电路仿真程序(HSPICE)的仿真结果表明,与先进的TNU加固锁存器设计相比,该锁存器的延迟平均降低了64.65%,延迟功耗面积积平均降低了65.07%。With the continuous development of nanoscale CMOS integrated circuits,latches are extremely susceptible to harsh radiation environment,and the multiple-node upset caused by radiation is becoming more and more serious.A Triple Node Upset(TNU)tolerant latch based on Dual-Interlocking CElls(DICEs)and dual-level C-elements is proposed.It includes five transmission gates,two DICEs,and three C-elements.The latch has a small number of transistors,which reduces greatly the hardware overhead of the latch to ensure low cost.Each DICE can be used to tolerate and recover from single-node upset,and the C-element has an error interception feature to mask erroneous values from DICEs.When any three nodes of the latch are upset,the latch can tolerate the TNU with the help of DICEs and C-elements.The simulation results using H-Simulation Program with Integrated Circuit Emphasis(HSPICE)show that,compared with the most advanced TNU tolerant latch designs,the delay is reduced by 64.65%,and the delay power area product is reduced by 65.07%for the proposed latch on average.

关 键 词：锁存器 3节点翻转 抗辐射加固技术 C单元 双联互锁存储单元 

分 类 号：TN43[电子电信—微电子学与固体电子学]