一种用于砷化镓晶圆级堆叠的工艺技术  

A Process Technology for GaAs Wafer-level Stacking

作　　者：廖龙忠[1] 周国[1] 毕胜赢 付兴中[1] 张力江[1] LIAO Longzhong;ZHOU Guo;BI Shengying;FU Xingzhong;ZHANG Lijiang(The 13th Research Institute,CETC,Shijiazhuang,050051,CHN)

机构地区：[1]中国电子科技集团公司第十三研究所,石家庄050051

出　　处：《固体电子学研究与进展》2023年第4期311-315,共5页Research & Progress of SSE

摘　　要：随着电子系统对多功能、小型化要求的不断提高,将数字控制电路、移相器、低噪声放大器等砷化镓微波集成电路(MMICs)进行3D集成是解决问题的方向。为此,设计具有数百个互连点的孔链测试结构模拟上下两层电路互连,采用砷化镓穿孔技术将正面互连压点转移到背面,研究适用砷化镓薄片的晶圆级键合技术,开发出两片式砷化镓面对背的晶圆级堆叠工艺技术,堆叠成品率达到90%以上。利用这项工艺,将砷化镓数字电路堆叠到低噪声放大器芯片上,形成了Ka波段幅相多功能电路,测试在32~38 GHz频段内,接收端增益大于21.5 dB,噪声小于4 dB,移相精度小于4°;发射端增益大于23 dB,输出功率大于25 dBm(输入功率10 dBm),移相精度小于4°。With increasing demand of the electronic systems for multi-function and miniaturiza⁃tion,the solution is the three-dimension(3D)integration which can integrate GaAs monolithic micro⁃wave integrated circuits(MMICs)like digital control circuits,phase shifters,low noise amplifiers and so on.In this paper,a test structure including hundreds of vias-chain was designed to imitate the cir⁃cuits on the layers which would be bonded.The pads on front surface were transferred to back surface by the through wafer vias technology which can vertical through GaAs substrate.The wafer to wafer(W2W)bonding technologies were optimized for thinned GaAs.The vertical wafer-level stacking technology was developed,which could bond two GaAs as face to back,and the assembly yield was over 90 percent.Finally,the Ka-band multi-function chip with phase and amplitude control was fabri⁃cated by assembling digital control circuit to low noise amplifier.At 32-38 GHz frequencies,the mea⁃sured results are as follows:In receiver,the gain is above 21.5 dB,the noise factor is below 4 dB,and the phase shift accuracy is below 4°;In transmitter,the gain is above 23 dB,the output power is above 25 dBm(input power of 10 dBm),and the phase shift accuracy is below 4°.

关 键 词：晶圆级堆叠技术 3D集成 砷化镓穿孔技术 幅相多功能电路 微波集成电路(MMICs) 

分 类 号：TN385[电子电信—物理电子学]