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作 者:韩子媛 王轩 秦靖尧 王瞧[2] 许岩 HAN Ziyuan;WANG Xuan;QIN Jingyao;WANG Qiao;XU Yan(PowerChina Henan Electric Power Survey&Design Institute Co.,Ltd.,Zhengzhou 450000,China;School of Electrical Engineering,Henan University of Technology,Zhengzhou 450001,China)
机构地区:[1]中国电建集团河南省电力勘测设计院有限公司,河南郑州450000 [2]河南工业大学电气工程学院,河南郑州450001
出 处:《电子设计工程》2023年第20期45-48,53,共5页Electronic Design Engineering
摘 要:针对5G智能电网的高精度时钟同步需求,提出一种主从节点时钟在线实时同步方法,并建立其数字实现模型。该方法采用一种由时差测量、时钟状态估计、环路滤波器和全数字时钟生成单元构成的时钟反馈控制环路。基于IEEE1588精确时间同步协议完成主从节点间的时差测量;根据时钟模型,建立时钟状态方程和观测方程,采用卡尔曼滤波对时钟状态进行估计;将时钟相位误差、频率误差作为一阶FLL辅助的PLL环路滤波器输入;环路滤波器输出控制量驱动调节从节点全数字时钟生成,以与主节点时钟保持在线实时同步。仿真结果表明,主从节点通信载噪比在65~95 dBHz范围内变化时,可实现主从节点间ns级的时钟同步精度。Aiming at the high⁃precision clock synchronization requirements of 5G smart grid,an online real⁃time clock synchronization method was proposed,and its digital implementation model was est⁃ablished.This method adopted a clock feedback control loop,which composed of time difference measurement,clock state estimation,loop filter and all digital clock generation unit.Time difference measurement was obtained based on IEEE1588 precise time synchronization protocol.According to the clock model,the clock state equation and observation equation were established,and the clock state was estimated based on Kalman filter.The clock phase error and frequency error were input to the PLL loop filter assisted by the first⁃order FLL;The slave node regulated the generation of all digital clock and kept online real⁃time synchronization with the master node clock.The simulation results showed that the ns level clock synchronization accuracy can be achieved when the carrier noise ratio changed in the range of 65~95 dBHz.
关 键 词:5G智能电网 时钟模型 卡尔曼滤波 环路滤波器 时钟同步
分 类 号:TN98[电子电信—信息与通信工程]
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