一种用于CPLD擦写寿命验证的设计  

Design for CPLD Program/Erase Cycles Verification

作　　者：顾小明 肖培磊[1] 唐勇 GU Xiaoming;XIAO Peilei;TANG Yong(China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214035,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《电子与封装》2023年第9期11-16,共6页Electronics & Packaging

摘　　要：近年来,国防等应用领域对电子元器件提出了国产化要求,自主设计的高性能复杂可编程逻辑器件(CPLD)应运而生。这些CPLD需要按照一定的标准流程进行筛选、考核,其中擦写寿命是一项重要的考核指标。阐述了采用集成开发环境及自动化测试机台对CPLD擦写寿命进行验证的不足之处,提出了一种CPLD擦写寿命验证装置的设计,经过实际检验,设计的装置稳定可靠,满足大批量器件的验证需求,提高了CPLD擦写寿命验证的效率。In recent years,domestic requirements have been put forward for electronic components in application fields such as national defense,and high-performance complex programmable logic devices(CPLDs)designed independently have emerged.These CPLDs need to be tested and selected according to a certain standard process,with program/erase cycles being an important assessment indicator.The shortcomings of using integrated development environment and automated testing machine to verify the CPLD program/erase cycles are described,and a design of CPLD program/erase cycles verification device is proposed.After practical testing,the designed device is stable and reliable,meeting the verification requirements of a large number of devices,and greatly improving the efficiency of CPLD program/erase cycles verification.

关 键 词：JTAG接口 配置码格式 多工位 并行工作 

分 类 号：TN406[电子电信—微电子学与固体电子学]