深亚微米SOI工艺高压ESD器件防护设计  

Deep Submicron SOI Process High Voltage ESD Device Protection Design

作　　者：朱琪[1] 黄登华 陈彦杰 刘芸含 常红 ZHU Qi;HUANG Denghua;CHEN Yanjie;LIU Yunhan;CHANG Hong(China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214035,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《电子与封装》2023年第9期45-49,共5页Electronics & Packaging

基　　金：江苏省博士后科研资助计划(2019K117);江苏省青年基金(BK20200167)。

摘　　要：绝缘体上硅(SOI)工艺具有隔离面积小、隔离性能良好等特点,在功率半导体领域已被广泛采用。基于深亚微米SOI工艺技术节点和100V以上高压器件的特性,高压静电放电(ESD)器件稳健性弱的问题已成为ESD防护设计的技术难点之一,高压ESD防护器件的选择和设计显得尤为重要。为了提升SOI工艺高压ESD器件的稳健性,结合静电放电时器件的特性和工作性能,对ESD防护器件进行了选择,设计了合适的器件尺寸,获得了良好的ESD能力。运用了该设计的一款驱动MOSFET的控制器电路,通过了4000V人体模型(HBM)的ESD测试,该设计在SOI工艺高压ESD器件防护稳健性的问题上取得了良好的效果。Silicon on insulator(SOI)process has the characteristics of small isolation area and good isolation performance,and has been widely adopted in the field of power semiconductors.Based on the deep submicron SOI process technology node and the characteristics of high voltage devices above 100 V,the problem of weak robustness of high voltage electrostatic discharge(ESD)devices has become one of the technical difficulties in the design of ESD protection,and the selection and design of high voltage ESD protection devices is particularly important.In order to improve the robustness of the high voltage ESD device of SOI process,the ESD protection device is selected by combining the characteristics and operating performance of the device during electrostatic discharge,and the appropriate device sizes are designed to obtain a good ESD capability.A controller circuit for driving MOSFET using the design has passed the 4000 V human body model(HBM)ESD test,and the design has achieved good results on the issue of robustness of high voltage ESDdevice protection for SOIprocess.

关 键 词：高压ESD器件 绝缘体上硅工艺 开放式基极堆叠三极管 

分 类 号：TN402[电子电信—微电子学与固体电子学]