一种面向多核独享L2 Cache的缓存一致性设计实现  

A Cache consistency design and implementation for multi-core private L2 Cache

作　　者：马良骥 杨靓[1] 肖建青[1] 娄冕[1] 赵翠华[1] MA Liangji;YANG Liang;XIAO Jianqing;LOU Mian;ZHAO Cuihua(Xi'an Microelectronics Technology Institute,Xi’an 710054,Shaanxi,China)

机构地区：[1]西安微电子技术研究所,陕西西安710054

出　　处：《微电子学与计算机》2023年第10期102-109,共8页Microelectronics & Computer

基　　金：总装某型谱项目(1905WJ0027_2)。

摘　　要：近年来,独享L2 Cache是实现高性能多核处理器的主流架构,但是该架构在维护Cache一致性上需要多次访存,增加了系统开销.为此,本文基于PowerPC指令架构实现了一种基于私有Cache状态机与片上总线监测机制相融合的多核缓存一致性设计,使处理器之间可以直接通过干涉接口交互数据.采用硬件描述语言Verilog HDL设计并实现了该多核缓存结构,仿真结果表明,在实现缓存一致性时,这种具有干涉路径的结构相比于传统访存方法最大能够节省87.06%的时间开销,有效地提升了多核处理器性能.最后经过实物芯片在板级上的测试,与仿真结果保持一致.In recent years,private L2 Cache is the mainstream architecture for high-performance multi-core processors,but it requires multiple memory accesses to maintain Cache consistency,which increases system overhead.Therefore,this paper proposes a multi-core Cache coherency design based on on PowerPC instruction architecture,which integrates private Cache state machine and on-chip bus monitoring mechanism,so that processors can directly exchange data through intervention interface.The multi-core Cache structure is designed and implemented by Verilog HDL,a hardware description language,and the simulation results show that when implementing Cache consistency,compared with the traditional memory access method,this structure with intervention path can save 87.06%time,and the performance of multi-core processor is effectively improved.Finally,the test results of real chip on board level are consistent with the simulation results.

关 键 词：多核一致性 独享L2 Cache PLB总线 干涉接口 

分 类 号：TN702[电子电信—电路与系统]