FinFETs based on layered 2D semiconductors  

作　　者：Theresia Knobloch Tibor Grasser 

机构地区：[1]Institute for Microelectronics,TUWien,Gusshausstrasse 27-29,1040 Vienna,Austria

出　　处：《Science China Materials》2023年第9期3759-3760,共2页中国科学（材料科学（英文版）

摘　　要：Over the past decades, the continued scaling of transistor dimensions, as dictated by Moore’s Law, has reduced energy consumption and increased the computational power of integrated circuits. At gate lengths below 12 nm, the scaling meets a physical limit, and as for ensuring reasonable gate control, a further reduction of the gate lengths requires scaling of the silicon thickness.

关 键 词：SCALING TRANSISTOR LAYERED 

分 类 号：TN386[电子电信—物理电子学]