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作 者:曹雪兵 CAO Xuebing(The 47th Institute of China Electronics Technology Group Corporation,Shenyang 110000,China)
机构地区:[1]中国电子科技集团公司第四十七研究所,沈阳110000
出 处:《微处理机》2023年第5期1-5,共5页Microprocessors
摘 要:针对纳米级工艺中存在的组合逻辑电路单粒子瞬态现象对电路可靠性的危害问题。通过采用基于延迟单元的双模冗余思想,在传统设计的基础上,提出一种改进的可以抗单粒子翻转和单粒子瞬态的带有扫描输入功能的TSPC型D触发器。该设计采用双模冗余结构实现抗单粒子翻转加固,通过引入延迟单元结构消除输入数据信号所产生的SET瞬态脉冲,并添加扫描输入功能增强触发器的灵活性与系统的可测性。通过UMC 55nm工艺软错误故障注入仿真,结果表明,所提出的电路结构能够有效抑制单粒子翻转和单粒子瞬态脉冲对D触发器可靠性的影响。Aiming at the harm of single event transient phenomenon of combinational logic circuit to circuit reliability in nano-scale process,based on the traditional design,an improved TSPC D flip-flop with scanning input function is proposed by adopting the dual-mode redundancy idea based on delay unit,which can resist single event inversion and single event transient.In the design,dual-mode redundant structure is adopted to realize anti-single-event overturning reinforcement,delay cell structure is introduced to eliminate the SET transient pulse generated by the input data signal,and scanning input function is added to enhance the flexibility of the trigger and the testability of the system.Through the simulation of soft error fault injection in UMC 55 nm process,the results show that the proposed circuit structure can effectively suppress the influence of single event flip-flop and single event transient pulse on the reliability of D flip-flop.
分 类 号:TN402[电子电信—微电子学与固体电子学]
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