基于Chipyard的RISC⁃V处理器设计与实现  

Design and implementation of RISC⁃V processor based on Chipyard

作　　者：谭飞鸿 苏成悦[1] Tan Feihong;Su Chengyue(School of Physics&Optoelectronic Engineering,Guangdong University of Technology,Guangzhou 510000,China)

机构地区：[1]广东工业大学物理与光电工程学院,广州510000

出　　处：《现代计算机》2023年第17期68-73,共6页Modern Computer

摘　　要：芯片设计领域的RISC⁃V较ARM、X86和PowerPC等主流指令集架构有着精简、开源和灵活的明显优势。利用Chipyard框架采用Chisel语言设计了五级流水线的RISC⁃V处理器兼具开发周期短和保留RISC⁃V的架构优势。其中,存储器管理单元(MMU)支持页面的虚拟内存和无阻塞数据缓存,并具备分支预测、浮点运算等功能,在FPGA上完成软硬件协同仿真。实验表明,基于Chipyard设计的RISC⁃V处理器支持RV64GC指令集集合,Dhrystone跑分达到1.27 DMIPS/MHz。RISC‑V in the field of chip design has obvious advantages of simplicity,open source and flexibility over mainstream instruction set architectures such as ARM,X86 and PowerPC.In this paper,a five‑level pipelined RISC‑V processor is designed by using Chipyard framework and Chisel language,which has the advantages of short development cycle and retaining RISC‑V architecture.Among them,the memory management unit(MMU)supports the virtual memory of pages and non‑blocking data cache,and has the functions of branch prediction,floating‑point operation and so on.Hardware and software co‑simulation is completed on FPGA.The experimental results show that the RISC‑V processor based on Chipyard supports RV64GC instruction set,and the Dhrystone run score is 1.27 DMIPS/MHz.

关 键 词：RISC⁃V Chipyard MMU 五级流水线 FPGA Dhrystone 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]