测试回路杂散电感消除技术研究  

Research on Eliminating Stray Inductance in Test Loops

作　　者：袁丽娟 荆茂盛 胡奇威 左宁[1] 王洪洲 YUAN Liyuan;JING Maosheng;HU Qiwei;ZUO Ning;WANG Hongzhou(The 45th Research Institute of CETC,Beijing 100176,China)

机构地区：[1]中国电子科技集团公司第四十五研究所,北京100176

出　　处：《电子工业专用设备》2023年第5期55-60,共6页Equipment for Electronic Products Manufacturing

摘　　要：由于测试回路中的杂散电感会在被测器件开通和关断的过程中感应出较高的电压尖峰,增大了被测器件的电压应力,严重影响被测器件相关参数的测试精度,甚至导致被测器件损坏。对高压探针测试系统测试回路中产生杂散电感的原理进行研究,通过仿真分析和优化设计,提出了一种在测试回路中采用叠层母排结构以降低杂散电感的解决办法。The stray inductance in the test loop con induce higher voltage spikes during the opening and closing of the device under test,which could increase the voltage stress of the device under test,seriously to affect the test accuracy of relevant parameters of the device under test,and even cause damage to the device under test.This paper studies the principle of generating stray inductance in the test loop of the high voltage probe testing system.by means of simulation analysis and optimization design,a solution to reduce stray inductance by using a stacked busbar structure in the test loop is proposed.

关 键 词：探针测试系统 杂散电感 叠层母排 

分 类 号：TN307[电子电信—物理电子学]