基于FPGA的UART自适应接收IP核设计  

Design of UART Adaptive Receiving IP Core Based on FPGA

作　　者：徐胜[1] 文丰[1] Xu Sheng;Wen Feng(National Key Laboratory for Electronic Measurement Technology,North University of China,Taiyuan 030051,China)

机构地区：[1]中北大学电子测试技术国家重点实验室,太原030051

出　　处：《单片机与嵌入式系统应用》2023年第11期14-16,20,共4页Microcontrollers & Embedded Systems

摘　　要：为解决串行传输时发送方波特率多变情况下接收方每次都需要与发送方进行波特率约定的问题,设计了UART自适应接收IP核,在FPGA内部设置波特率库,利用0校验位和空闲位持续时间准确识别波特率,实现了UART的自适应接收,同时基于VHDL将整个模块封装为IP核,进一步提高了设计的通用性。通过Vivado内部仿真工具进行仿真,仿真结果表明,本设计可以在设置的波特率库下进行UART的自适应接收。In order to solve the problem that the receiver needs to make baud rate agreement with the sender every time when the sender's baud rate is variable during serial transmission,the UART adaptive reception IP core is designed in the paper.The baud rate li-brary inside the FPGA is set up,and accurately identifies the baud rate by using the 0 check digit and the duration of the idle bit,reali-zing the adaptive reception of the UART.At the same time,the whole module is encapsulated into an IP core based on VHDL,which fur-ther improves the generality of the design.The simulation is performed by Vivado internal simulation tool,and the results show that this design can perform adaptive reception of UART under the set baud rate library.

关 键 词：FPGA 波特率库 自适应接收 串行通信 IP核 

分 类 号：TN919.3[电子电信—通信与信息系统]