Chiplet异构集成微系统的EDA工具发展综述  

A review of EDA tool development for Chiplet heterogeneous integrated microsystems

作　　者：郭继旺 尹文婷 谈玲燕 王宗源 GUO Jiwang;YIN Wenting;TAN Lingyan;WANG Zongyuan(Empyrean Technology Co.,Ltd.,Beijing 100102,China)

机构地区：[1]北京华大九天科技股份有限公司,北京100102

出　　处：《微电子学与计算机》2023年第11期53-60,共8页Microelectronics & Computer

摘　　要：Chiplet(芯粒)异构集成微系统是后摩尔时代背景下一项具有重要意义的技术趋势.随着芯粒技术的不断发展,芯粒数量越来越多,三维立体化的集成度越来越高,芯粒方案的面积也越来越大.而目前Chiplets设计流程中各环节的电子设计自动化(EDA)工具发挥的支撑作用还比较有限.通过剖析现有Chiplets设计流程在系统规划、单芯片设计、基板设计、微系统集成分析和验证等环节存在的缺陷和不足,以及国产EDA技术在interposer工艺设计套件(PDK)开发、芯粒设计布局规划、高效自动布线、多芯片集成分析和物理验证等板块的应用现状,指出了当前Chiplet设计面临着物理验证不规范、布线效率低下和缺乏涵盖多物理场耦合的集成分析等痛点.面对3DIC未来发展对EDA工具提出的更多挑战,提出了市场上迫切需要的芯片-封装协同设计解决方案.Chiplet heterogeneous integrated microsystems are a significant technological trend in the post Moore era.With the continuous development of Chiplet technology,the number of Chiplets is increasing,the integration degree of 3D visualization is becoming higher,and the area of Chiplets solutions is also increasing.At present,the supporting role of electronic design automation(EDA)tools in various stages of the Chiplets design process is still relatively limited.By analyzing the defects and deficiencies of the existing Chiplets design process in system planning,single-chip design,substrate design,microsystem integration analysis and verification,and the current application status of domestic EDA technology in interposer process design kit(PDK)development,Chiplets design layout planning,efficient automatic routing,multi-chip integrated analysis and physical verification,it was pointed out that the current Chiplet design faces pain points such as non-standard physical verification,inefficient routing and lack of integrated analysis covering multiphysics coupling.Faced with more challenges posed by the future development of 3DIC for EDA tools,a chip-packaging collaborative design solution urgently needed in the market has been proposed.

关 键 词：Chiplet 异构集成 EDA 微系统 

分 类 号：TN402[电子电信—微电子学与固体电子学]