一种基于40 nm CMOS工艺的25 Gb/s新型CTLE电路  

New 25 Gb/s CTLE circuit based on 40 nm CMOS process

作　　者：李博恺 何进[1] LI Bokai;HE Jin(School of Physics and Technology,Wuhan University,Wuhan 430072,China)

机构地区：[1]武汉大学物理科学与技术学院,武汉430072

出　　处：《光通信技术》2023年第6期32-37,共6页Optical Communication Technology

基　　金：国家自然科学基金项目(批准号:61774113)资助。

摘　　要：为了解决传统连续时间线性均衡器(CTLE)均衡能力较差的问题,提出了一种基于40 nm互补金属氧化物半导体(CMOS)工艺的25 Gb/s新型CTLE电路,该电路采用并联电感峰化、负电容零点补偿和输出缓冲技术。介绍了并联电感峰化及无源器件对CTLE频率特性的影响,最后对新型CTLE电路进行了仿真。仿真结果表明:在数据传输速率为25 Gb/s时,该CTLE电路均衡后的-3 dB带宽从8.5 GHz拓展到21.3 GHz;输出信号眼图的差分电压峰峰值为410 mV,功耗为8.62 mW;整体电路版图面积为667μm×717μm,具备功耗低和面积小的特点。In order to solve the problem of poor equalization ability of traditional continuous time linear equalizer(CTLE),a new 25 Gb/s CTLE circuit based on 40 nm complementary metal oxide semiconductor(CMOS)technology is proposed,which adopts parallel inductance peaking,negative capacitance zero compensation and output buffering technology.The influence of shunt inductance peaking and passive devices on CTLE frequency characteristics is introduced.Finally,the new CTLE circuit is simulated.The simulation results show that when the data transmission rate is 25 Gb/s,the equalized bandwidth of the CTLE extends from 8.5 GHz to 21.3GHz.The peak-to-peak differential voltage of the output signal is 410 mV,and the power consumption is 8.62 mW.The overall circuit layout area is 667μm×717μm,which has the characteristics of low power consumption and small area.

关 键 词：高速光通信 连续时间线性均衡器 电感峰化 负电容补偿 互补金属氧化物半导体 

分 类 号：TN432[电子电信—微电子学与固体电子学]