异构双核处理器失速告警系统设计  

Design of Heterogeneous Dual-Core Processor Stall Warning System

作　　者：魏璐达 宣晓刚 杨飞 张美仙 贾少龙 WEI Luda;XUAN Xiaogang;YANG Fei;ZHANG Meixian;JIA Shaolong(AVIC Taiyuan Aero-Instruments Co.,Ltd.,Taiyuan 030006,China)

机构地区：[1]航空工业太原航空仪表有限公司,山西太原030006

出　　处：《自动化仪表》2023年第12期26-30,36,共6页Process Automation Instrumentation

基　　金：山西省关键核心技术和共性技术研发攻关专项基金资助项目(2020XXX019)。

摘　　要：失速会影响飞机飞行安全。传统的失速告警系统虽然通过采用多处理器同步时钟的方法提高了安全性,但系统可靠性降低且复杂度变高。为提升失速告警系统的可靠性、降低失速告警系统的复杂度,采用异构双核处理器所具备的核间数据交互和数据一致性检查功能来实现失速告警系统的高安全性设计。首先,依据总体设计选择合适的处理器。然后,根据所选的异构双核处理器对核间通信机制进行对比选择。最后,对双核数据传输任务进行合理分配。测试结果表明,利用双核处理器中的共享内存通信机制进行数据传输,数据的传输交互更加安全、快速和高效。通过对解算数据在同一处理器进行一致性检查的方法,提高了输出指令的正确率,提升了系统的安全性能,满足了失速告警系统对于高可靠性、高安全性的要求。此外,选用异构双核处理器进行余度设计同样适用于其他类型系统。Stall affects the safety of aircraft flight. Although the traditional stall warning system improves the safety by adopting the method of synchronizing the clock of multi-processors, the reliability of the system is reduced, and the complexity becomes high. To improve the reliability and reduce the complexity of the stall warning system, the inter-core data interaction and data consistency checking functions of heterogeneous dual-core processors are used to realize the high security design of the stall warning system. Firstly, a suitable processor is selected based on the overall design. Then, the inter-core communication mechanism is compared and selected based on the selected heterogeneous dual-core processor. Finally, the dual-core data transmission tasks are reasonably assigned. The test results show that by utilizing the shared memory communication mechanism in the dual-core processor for data transfer, the data transfer interaction is safer, faster, and more efficient. The method of consistency checking to the solved data in the same processor improves the correctness of the output instructions, enhances the safety performance of the system, and meets the requirements of the stall alarm system for high reliability and high security. In addition, the selection of heterogeneous dual-core processors for residual design is also applicable to other types of systems.

关 键 词：失速 告警系统 余度 虚警率 双核处理器 共享内存 数据一致性 安全性 

分 类 号：TH702[机械工程—仪器科学与技术]