Flash型FPGA内嵌BRAM测试技术研究  

Research on Test Technology of Embedded BRAM in Flash-Based FPGA

作　　者：雷星辰 季伟伟 陈龙 韩森 LEI Xingchen;JI Weiwei;CHEN Long;HAN Sen(Shenzhen Institute for Advanced Study,University of Electronic Science and Technology of China,Shenzhen 518110,China;China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214035,China)

机构地区：[1]电子科技大学(深圳)高等研究院,广东深圳518110 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《电子与封装》2023年第12期14-19,共6页Electronics & Packaging

摘　　要：Flash型FPGA由于具有高可靠性、卓越的安全性和即插即用的功能,被广泛应用于军事及航空航天领域。Flash型FPGA的内部结构复杂而庞大,因此研究其测试技术的可靠性和准确性至关重要。块随机存储器(BRAM)作为FPGA内部重要的存储模块,在传统测试中存在故障覆盖率较低的问题。为了扩大故障覆盖范围,对March C+算法进行了改进,优化后算法对写干扰故障(WDF)、写破坏耦合故障(CFwd)、干扰耦合故障(CFds)和字内耦合故障的检测能力得到了显著提高。结果表明,优化后的算法相较于March C+算法,其故障覆盖率提高了25个百分点,且与时间复杂度相同的March SS算法相比,其故障覆盖率提高了5.8个百分点。Flash-based FPGAs are widely used in military and aerospace fields due to their high reliability,excellent security and plug-and-play functionality.Internal structures of Flash-based FPGAs are complex and bulky,so it is crucial to study the reliability and accuracy of their test technologies.Block random access memory(BRAM),as an important internal storage module of FPGA,has the problem of low fault coverage in traditional tests.In order to expand the coverage of faults,the March C+algorithm is improved,and the optimized algorithm significantly improves the detection ability of write disturb fault(WDF),write destructive coupling fault(CFwd),disturb coupling fault(CFds)and intra-word coupling fault.The results show that the optimized algorithm improves the fault coverage by 25 percentage points compared to the March C+algorithm and by 5.8 percentage points compared to the March SS algorithm with the same time complexity.

关 键 词：Flash型FPGA March C+算法 BRAM 

分 类 号：TN402[电子电信—微电子学与固体电子学]