一种三环结构高效率的数字LDO电路  

A high-efficiency tri-loop architecture digital LDO circuit

作　　者：徐洪 韦保林[1] 宣艳[2] 徐卫林[1] 韦雪明[1] 李海鸥[1] 段吉海[1] XU Hong;WEI Baolin;XUAN Yan;XU Weilin;WEI Xueming;LI Haiou;DUAN Jihai(Key Laboratory of Microelectronic Devices and Integrated Circuits,Guilin University of Electronic Technology,Guilin 541004,China;Guodian Nanrui Technology Co.,Ltd,Nanjing 211106,China)

机构地区：[1]桂林电子科技大学广西高校微电子器件与集成电路重点实验室,广西桂林541004 [2]国电南瑞科技股份有限公司,江苏南京211106

出　　处：《微电子学与计算机》2023年第12期110-116,共7页Microelectronics & Computer

基　　金：国家自然科学基金(61861009);广西无线宽带通信与信号处理重点实验室主任基金(GXKL06200105);广西创新研究团队项目(2018GXNSFGA281004);桂林电子科技大学研究生科研创新项目(2021YCXS047)。

摘　　要：设计了一种采用0.18µm互补金属氧化物半导体(CMOS)工艺制作的三环结构无片外电容数字低压差线性稳压器(LDO)电路,主要在控制方式进行创新,针对不同的输出电压范围采取相应的环路进行调整.电路的功率MOS管阵列按MOS管尺寸,分为大(L)、中(M)、小(S)3组,设计的控制方式使环路可根据负载变化迅速切换,使得电路具有快速的瞬态响应,较强的带负载能力,较低的输出电压纹波和功耗,转换效率最高可达88.9%.在1.8 V输入电压下的后仿真结果表明,负载电流在2~60 mA之间突变时,电路的下冲电压为95 mV,过冲电压为80 mV,恢复时间小于1.7µs,稳态下的输出电压纹波小于2.0 mV,总体静态电流约为43µA.该数字LDO的输入电压范围为1~1.8 V,输出电压范围为0.8~1.6V,内部集成10pF电容,品质因素FOM仅为0.009pF.A tri-loop structure digital Low DropOut Regulator(LDO)circuit without off-chip capacitors fabricated by 0.18µm Complementary Metal Oxide Semiconductor(CMOS)process is designed,the main innovation is in the control method,and the corresponding loop adjustment is adopted for different output voltage ranges.Its power MOSFET(Metal Oxide Semiconductor Field Effect Transistor)array is divided into three groups,that is large(L),medium(M)and small(S)according to the size of the MOS tube.The designed control method allows the loop to switch quickly according to the load change,so that the circuit has a fast transient response.Strong load capacity,low output voltage ripple and power consumption,and the highest conversion efficiency is 88.9%.The post-simulation results under the input voltage of 1.8 V show that when the load current suddenly changes between 2 mA and 60 mA,the undershoot voltage of the circuit is 95 mV,the overshoot voltage is 80 mV,and the stabilization time is less than 1.7µs.The voltage ripple is less than 2.0 mV and the overall quiescent current is about 43µA.The input voltage range of this digital LDO is 1-1.8 V,and the output voltage range is 0.8-1.6 V.The internal 10 pF capacitor is integrated,and the quality factor FOM is only 0.009 pF.

关 键 词：三环结构 低压差线性稳压器 低输出电压纹波 无片外电容 带负载能力强 数字集成电路 

分 类 号：TN432[电子电信—微电子学与固体电子学]