基于FPGA的TANGRAM分组密码算法实现  

Implementation of TANGRAM block cipher algorithm based on FPGA

作　　者：王建新[1] 许弘可 郑玉崝 肖超恩[1] 张磊[1] 洪睿鹏 Wang Jianxin;Xu Hongke;Zheng Yuzheng;Xiao Chao’en;Zhang Lei;Hong Ruipeng(Beijing Electronic Science&Technology Institute,Beijing 100070,China)

机构地区：[1]北京电子科技学院,北京100070

出　　处：《计算机应用研究》2024年第1期260-265,共6页Application Research of Computers

基　　金：教育部新工科研究与实践项目(E-AQGABQ20202704);北京高等教育“本科教学改革创新项目”(202110018002);北京电子科技学院一流学科建设项目(20210064Z0401,20210056Z0402);中央高校基本科研业务费资金资助项目(328202205,328202271,328202269);国家重点研发计划基金资助项目(2017YFB0801803)。

摘　　要：TANGRAM系列分组密码算法是一种采用比特切片方法,适合多种软硬件平台的系列分组密码算法。针对TANGRAM-128/128算法,使用Verilog HDL对该算法进行FPGA实现并提出设计方案。首先,介绍了TANGRAM密码算法的特点和流程,提出了针对TANGRAM密码算法进行44轮加/解密迭代计算的方案,该方案采取有限状态机的方法有效降低了资源消耗;其次,基于国产高云云源平台,完成了基于高云FPGA的算法工程实现,以及功能仿真和数据的正确性验证,同时在QuartusⅡ13.1.0平台上也进行了相关测试,用以比较。测试结果表明,TANGRAM系列分组密码算法基于Altera公司的CycloneⅣE系列EP4CE40F29C6芯片进行工程实现,最大时钟频率为138.64 MHz,加/解密速率为403.30 Mbps;基于高云半导体GW2A-55系列芯片的最大时钟频率为96.537 MHz,加/解密速率为280.80 Mbps。TANGRAM block cipher algorithm employs a bit-slice approach and is compatible with multiple software and hardware platforms.In response to TANGRAM-128/128 algorithm,this paper proposed a design plan which used Verilog HDL for FPGA implementation.This paper firstly provided an introduction to the characteristics and processed of TANGRAM algorithm and presented a scheme for reducing resource consumption using a finite-state machine for 44 rounds of encryption and decryption computation.Secondly,the engineering implementation of the FPGA algorithm was completed by the domestic Gaoyun platform and subjected to functional simulation and data correctness validation.Furthermore,relevant tests were performed on QuartusⅡ13.1.0 platform for comparison.Test results show that,based on Cyclone IV E EP4CE40F29C6 chip from Altera,TANGRAM block cipher algorithm has a maximum clock frequency of 138.64 MHz and an encryption/decryption speed of 403.30 Mbps.While based on the GW2A-55 chip from Gaoyun,the maximum clock frequency is 96.537 MHz and the encryption/decryption speed is 280.80 Mbps.

关 键 词：TANGRAM 分组密码算法 Verilog HDL 有限状态机 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]