基于共享总线结构的存储器内建自测试电路  

Memory Built-in Self-Test Circuit Based on Shared Bus

作　　者：雷鹏 纪元法[1] 肖有军 李尤鹏 Lei Peng;Ji Yuanfa;Xiao Youjun;Li Youpeng(School of Information and Communication,Guilin University of Electronic Technology,Guilin 541004,China;Global Unichip Corp(Nanjing),Nanjing 210018,China)

机构地区：[1]桂林电子科技大学信息与通信学院,广西桂林541004 [2]创意电子(南京)有限公司,南京210018

出　　处：《半导体技术》2024年第2期158-163,200,共7页Semiconductor Technology

基　　金：国家自然科学基金(62061010,62161007);广西科技厅项目(桂科AA20302022,桂科AB21196041,桂科AB22035074,桂科AD22080061);广西八桂学者项目;广西高校中青年教师科研基础能力提升项目(2022KY0181);桂林市科技项目(20210222-1);桂林电子科技大学研究生创新项目;“认知无线电与信息处理”教育部重点实验室2022年主任基金。

摘　　要：随着片上系统处理的数据增多,数据存储器测试逻辑相应增加,在保证测试功能的同时减小测试电路面积是当下急需解决的问题。基于共享总线结构的存储器内建自测试(MBIST)电路,通过将多个存储器引脚信号进行复用的方式,对存储器进行层次化设计,将物理存储器拼接组成逻辑存储器模块,再整合多个逻辑存储器成为一个大的存储器集模块,MBIST控制器针对存储器集进行MBIST,从而减少测试逻辑数量以达到减小测试电路占用面积的目的。通过实验证明,该结构可以满足MBIST相关需求,相较于针对单颗存储器测试的传统MBIST电路面积减小了21.44%。该方案具有良好的实用性,可以为相关存储器测试设计提供参考。With the increase of the amount of data processed by system on chip,the testing logics of data memory have increased accordingly.Reducing the testing circuit area while ensuring testing functionality is an urgent problem that needs to be solved currently.Memory built-in self-test(MBIST)circuit based on a shared bus was designed hierarchically by reusing signals from multiple memory pins.Physical memories were concatenated into a logical memory module,and multiple logic memories were then integrated into a large memory cluster module.The MBIST controller performed MBIST on these memory clusters,thereby reducing the number of testing logics to achieve the goal of reducing the testing circuit area.Through experiments,it is proven that this structure can meet the MBIST related requirements,which reduces the circuit area by 2144%compared with traditional MBIST circuits for single memory testing.This scheme has good practicality and can provide reference for related memory testing design.

关 键 词：共享总线结构 存储器内建自测试(MBIST) 逻辑存储器 测试电路面积 层次化设计 

分 类 号：TP333.8[自动化与计算机技术—计算机系统结构]