A Study on the Design Method of Hybrid MOSFET-CNTFET Based SRAM-A Secondary Publication  

作　　者：Geunho Cho 

机构地区：[1]Department of Electronic Engineering,Seokyeong University,Seoul,South Korea

出　　处：《Journal of Electronic Research and Application》2024年第1期106-112,共7页电子研究与应用

基　　金：supported by Seokyeong University in 2022.The EDA tool was supported by the IC Design Education Center(IDEC),Korea.

摘　　要：More than 10,000 carbon nanotube field-effect transistors(CNTFETs)have been successfully integrated into one semiconductor chip using conventional semiconductor design procedures and manufacturing processes.These transistors offer advantages such as high carrier mobility,large saturation velocity,low intrinsic capacitance,flexibility,and transparency.The three-dimensional multilayer structure of the CNTFET semiconductor chip,along with ongoing research in CNTFET manufacturing processes,increases the potential for creating a hybrid MOSFET-CNTFET semiconductor chip.This chip combines conventional metal-oxide-semiconductor field-effect transistors(MOSFETs)and CNTFETs in one integrated system.This paper discusses a methodology to design 6T binary static random-access memory(SRAM)using a hybrid MOSFET-CNTFET.This paper introduces a method for designing a hybrid MOSFET-CNTFET SRAM by leveraging existing MOSFET SRAM or CNTFET SRAM design approaches.Additionally,this paper compares its performance with conventional MOSFET SRAM and CNTFET SRAM designs.

关 键 词：MOSFET CNTFET SRAM HYBRID Carbon nanotube 

分 类 号：TN3[电子电信—物理电子学]