基于FPGA的8B/10B编解码IP核设计  

Design of 8B/10B Encoder and Decoder IP Core Based on FPGA

作　　者：周爽 周莉 ZHOU Shuang;ZHOU Li(National Space Science Center,Chinese Academy of Sciences,Beijing 100190,China;School of Computer Science and Technology,University of Chinese Academy of Sciences,Beijing 101499,China)

机构地区：[1]中国科学院国家空间科学中心,北京100190 [2]中国科学院大学计算机科学与技术学院,北京101499

出　　处：《仪表技术与传感器》2023年第12期25-28,36,共5页Instrument Technique and Sensor

基　　金：中国科学院国家重大科技专项(E16505B31S)。

摘　　要：8B/10B编码技术将数据和时钟合并传输,有效减少电缆数量,广泛应用于质量体积受限的航天器上。针对FPGA自带的8B/10B IP核受版权限制、代码不透明的问题,设计了一个自主可控、移植性好、运行速率高、可靠性强的8B/10B编解码的IP核,除时钟外基于逻辑设计,其中编解码模块采用5B/6B与3B/4B 2个查找表降低资源占用,在解码端选取同频多相采样方法实现时钟与数据的恢复,有效降低解码器的采样频率。最后采用航天上常用的Virtex-4、Virtex-5和Kintex-7系列的FPGA进行误码率测试,在80 Mbps的通信速率下误码率小于10-9,验证了IP核设计的可靠性。8B/10B coding technology combined data and clock transmission,effectively reduce the number of cables,and is widely used in spacecrafts with limited mass volume.In view of the problem that the 8B/10B IP core of the FPGA is limited by copyright and the code is opaque,an 8B/10B encoder and decoder IP core is proposed in this paper,which is autonomous and controllable,has good portability,high running speed and strong reliability.Logic-based design in addition to the clock,two look-up tables,5B/6B and 3B/4B,were adopted to reduce resource consumption in encoding and decoding module.Multi-phase with the same frequency sampling method was used to achieve clock and data recovery and decrease the sampling frequency of the de-coder.Finally,the reliability of the IP core design was verified by conducting a bit-error-rate(BER)test on the Virtex-4,Virtex-5,and Kintex-7 series FPGA,which shows that the BER was less than 10-9 at the communication rate of 80 Mbps.

关 键 词：8B/10B编解码 时钟与数据恢复 同频多相采样 FPGA 

分 类 号：TN492[电子电信—微电子学与固体电子学]