一种基于二进制重组加权定制电容阵列的SAR ADC设计  

Design of SAR ADC Based on Binary Recombination Weighted Custom Capacitor Array

作　　者：林金晖 王宇 王法翔[1] LIN Jinhui;WANG Yu;WANG Faxiang(School of Physics and Information Engineering,Fuzhou University,Fujian 350116,China)

机构地区：[1]福州大学物理与信息工程学院,福建350116

出　　处：《集成电路应用》2023年第12期18-22,共5页Application of IC

摘　　要：阐述DAC电容阵列的不完全建立对SAR ADC的影响,设计一种基于二进制重组加权算法的SAR ADC,降低DAC电容对于建立时间和精度的要求。提出一种可变延时单元来调整比较器的时钟信号,以提高SAR ADC的转换速度。同时设计定制金属-氧化物-金属(MOM)电容,提高了电容阵列的密度,实现了线性度和面积的良好折中。基于上述技术,实现一种8bit 50Msps的SAR ADC,该电路基于SMIC0.18μm工艺实现。仿真结果表明,在1.8V电源电压和50Msps的采样频率下,电路的SNDR为47.49dB,ENOB可达7.6bit,功耗为3.6mW,有效电路面积仅为0.2141mm^(2)。This paper describes the impact of incomplete establishment of DAC capacitor array on SAR ADC,and designs a SAR ADC based on binary recombination weighting algorithm to reduce the requirements of DAC capacitor for establishment time and accuracy.It proposes a variable delay unit to adjust the clock signal of the comparator to improve the conversion speed of SAR ADC.Simultaneously designing custom metal oxide metal(MOM)capacitors has increased the density of the capacitor array,achieving a good compromise between linearity and area.Based on the above technology,it implements an 8bit 50Msps SAR ADC,which is based on SMIC 0.18μm process implementation.The simulation results show that at a power supply voltage of 1.8V and a sampling frequency of 50Msps,the SNDR of the circuit is 47.49dB,the ENOB can reach 7.6 bits,the power consumption is 3.6mW,and the effective circuit area is only 0.2141mm2.

关 键 词：集成电路设计 SAR ADC 二进制重组冗余 定制电容 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN792