Litho-Asym Vnet:super-resolution lithography modeling with an asymmetric V-net architecture  

作　　者：Qing ZHANG Yuhang ZHANG Wei LU Huajie HUANG Zheng ZHONG Congshu ZHOU Yongfu LI 

机构地区：[1]Department of Micro-Nano Electronics and MoE Key Lab of Artificial Intelligence,Shanghai Jiao Tong University,Shanghai 200240,China [2]Primarius Technologies Co.,Ltd.,Shanghai 201306,China

出　　处：《Science China(Information Sciences)》2023年第12期297-298,共2页中国科学（信息科学）（英文版）

基　　金：supported by National Natural Science Foundation of China (Grant Nos.62141414,62350610271)。

摘　　要：Lithography simulation is key to the preparation of mask data and verification of mask patterns[1],which enhances design-to-wafer fidelity and minimizes distortions.However,the complexity of lithography simulation has tremendously increased with the decrease in feature size,prolonging the simulation cycle.Hence,an accurate and fast lithography simulation is in great demand.

关 键 词：LITHOGRAPHY RESOLUTION ASYMMETRIC 

分 类 号：TN305.7[电子电信—物理电子学]