低插入损耗的5~14 GHz慢波时延器芯片设计  

Design of a 5-14 GHz Slow-wave Time-delay Chip with Low Insertion Loss

作　　者：全琪琪 戴新峰[1] 沈一鸣[1] 周光辉 QUAN Qiqi;DAI Xinfeng;SHEN Yiming;ZHOU Guanghui(Nanjing Electronic Device Institute,Nanjing,210016)

机构地区：[1]南京电子器件研究所,南京210016

出　　处：《固体电子学研究与进展》2024年第1期29-33,共5页Research & Progress of SSE

摘　　要：基于0.15μm E/D pHEMT工艺,设计了一款新型慢波线结构的时延器芯片。该时延器芯片集成了慢波时延线、单刀双掷开关和数字驱动器等功能芯片,其中,慢波时延线通过电磁仿真软件优化慢波结构的长度、间距以及拐角的结构,可以优化时延器的性能,提高集成度;单刀双掷开关采用具有高隔离度和低损耗的串并混合结构;数字驱动器采用高度集成pHEMT工艺,稳定输出两路反相电平。在片测试结果表明:在5~14 GHz频段内,芯片总插入损耗小于8.5 dB,中心频点延时量850 ps,输入输出驻波小于1.7,寄生调幅小于±0.8 dB,静态功耗1 mA@-5 V。芯片版图面积为6.7 mm×5.0 mm。A design of new structure of slow wave time-delay chip is shown in this paper.It was developed and tested based on 0.15μm E/D pHEMT process.Slow wave time-delay,single pole double throw switch and digital driver were integrated.The electromagnetic simulation software was used to optimize the length,space and corner structure of the slow-wave structure,which could opti-mize the time-delay performance and improve integration;a series-parallel hybrid structure with high isolation and low insertion loss was adopted in the single pole double throw switch;a highly integra-tion pHEMT process was used in the digital driver,which could achieve two stable output phase oppo-sitional voltages.The on-chip test results show that the insertion loss is less than 8.5 dB,the time de-lay is up to 850 ps,the VSWR is less than 1.7,the amplitude error is less than±0.8 dB at 5-14 GHz and the static power consumption is 1 mA@-5 V.The size of the chip is 6.7mm×5.0 mm.

关 键 词：低损耗 慢波线 时延器 

分 类 号：TN45[电子电信—微电子学与固体电子学] TN432