Physical insights into trapping effects on vertical GaN-on-Si trench MOSFETs from TCAD  

作　　者：NicolòZagni Manuel Fregolent Andrea Del Fiol Davide Favero Francesco Bergamin Giovanni Verzellesi Carlo De Santi Gaudenzio Meneghesso Enrico Zanoni Christian Huber Matteo Meneghini Paolo Pavan 

机构地区：[1]Department of Engineering“Enzo Ferrari”,University of Modena and Reggio Emilia,Modena 41125,Italy [2]Department of Information Engineering,University of Padova,Padova 35131,Italy [3]Department of Sciences and Methods for Engineering(DISMI),University of Modena and Reggio Emilia,Reggio Emilia 42122,Italy [4]EN&TECH Center,University of Modena and Reggio Emilia,Reggio Emilia 42122,Italy [5]Advanced Technologies and Micro Systems Department,Robert Bosch GmbH,Renningen 71272,Germany

出　　处：《Journal of Semiconductors》2024年第3期45-52,共8页半导体学报（英文版）

基　　金：funding from the Electronic Component Systems for European Leadership Joint Undertaking (ECSEL JU),under grant agreement No.101007229;support from the European Union’s Horizon 2020 Research and Innovation Programme,Germany,France,Belgium,Austria,Sweden,Spain,and Italy

摘　　要：Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications.Being still in an early development phase,vertical GaN devices are yet to be fully optimized and require careful studies to foster their development.In this work,we report on the physical insights into device performance improvements obtained during the development of vertical GaN-on-Si trench MOSFETs(TMOS’s)provided by TCAD simulations,enhancing the dependability of the adopted process optimization approaches.Specifically,two different TMOS devices are compared in terms of transfer-curve hysteresis(H)and subthreshold slope(SS),showing a≈75%H reduction along with a≈30%SS decrease.Simulations allow attributing the achieved improvements to a decrease in the border and interface traps,respectively.A sensitivity analysis is also carried out,allowing to quantify the additional trap density reduction required to minimize both figures of merit.

关 键 词：vertical GaN trench MOSFET SiO_(2) interface traps border traps HYSTERESIS BTI 

分 类 号：TN386[电子电信—物理电子学]