软硬协同的嵌入式系统存储可靠性增强设计  

Soft-Hardware Coordinated Design for Enhanced Storage Reliability in Embedded Systems

作　　者：杨渊 邹祖伟 YANG Yuan;ZOU Zuwei(Institute of Electronic Engineering,China Academy of Engineering Physics,Mianyang Sichuan 621999,China)

机构地区：[1]中国工程物理研究院电子工程研究所,四川绵阳621999

出　　处：《太赫兹科学与电子信息学报》2024年第2期219-226,共8页Journal of Terahertz Science and Electronic Information Technology

基　　金：国防科工局基础科研资助项目(JCKY2019212B004)。

摘　　要：单粒子翻转(SEU)效应是造成空天环境中处理器故障的常见原因,需进行有效的防护设计,提升航空航天等高空设备的可靠性。传统的嵌入式可靠性防护设计一般采用单一的硬件或软件方法:采用软件三模冗余实现,需要占用大量的中央处理器(CPU)资源;采用硬件电路实现,无法输出错误信息。以PPC460处理器为目标系统,探讨了利用现场可编程门阵列(FPGA)对PPC460处理器的可靠性增强设计方法,同时使用扩展型的汉明码编解码算法、奇偶校验、三模冗余技术,利用软硬协同的方式提高了存储空间内数据的正确性,减少了CPU资源消耗,有效实现了PPC460处理器在特殊复杂环境中对重要数据的高安全、高可靠、抗干扰保护。Single Event Upset(SEU)effects are a common cause of processor failures in aerospace environments,necessitating effective protective designs to enhance the reliability of high-altitude equipment in the fields of aviation and astronautics.Traditional embedded reliability protection designs typically employ either single hardware or software approaches:implementing Triple Modular Redundancy(TMR)through software requires substantial CPU resources;employing hardware circuits does not facilitate error reporting.This paper focuses on the PPC460 processor as the target system,discussing an advanced reliability enhancement design method utilizing Field-Programmable Gate Array(FPGA)technology for the PPC460 processor.The approach integrates an extended Hamming code encoding and decoding algorithm,parity checking,and Triple Modular Redundancy techniques.By synergistically combining software and hardware strategies,it improves the correctness of data within the storage space,reduces CPU resource consumption,and effectively realizes high-security,high-reliability,and interference-resistant protection for critical data on the PPC460 processor in special complex environments.

关 键 词：现场可编程门阵列(FPGA) 单粒子翻转 汉明码 三模冗余 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]