一种快速实现时序收敛的设计方法  

A design methodology for fast timing closure

作　　者：王虎虎 雷倩倩[1] 刘露 杨延飞 李连碧[1] 冯松[1] WANG Huhu;LEI Qianqian;LIU Lu;YANG Yanfei;LI Lianbi;FENG Song(School of Science,Xi'an Polytechnic University,Xi'an 710048,China)

机构地区：[1]西安工程大学理学院,陕西西安710048

出　　处：《微电子学与计算机》2024年第4期123-131,共9页Microelectronics & Computer

基　　金：国家重点研发计划(2018YFB2200500);陕西省重点研发计划(2022GY-012)。

摘　　要：为了解决处理器时序收敛困难和设计时间长的问题,本文基于14 nm的定制化处理器(WS_CPU)提出了一种高效可靠的设计方法:(1)基于一种新型的FCHT(Flexible Configurable H-Tree)时钟结构,实现时钟信号均匀分配和减少绕线时间,同时采用CCOPT(Clock Concurrent Optimization)技术进行时钟树综合优化;(2)在综合阶段采用DCG(Design Compiler Graphical)模式和门控时钟插入技术,提前评估设计风险从而减少布局布线的迭代时间。验证结果表明,当WS_CPU时钟频率为1 GHz时,寄存器之间建立时间的时序余量为108 ps,有效地实现了时序快速收敛,同时FCHT结构相比传统平衡树、柔性H树、3级H树的芯片总功耗分别减少了7.71%、6.18%、7.87%;FCHT时钟结构相比传统平衡树在时序修复上节省了3156 min,相比柔性H树节省了5220 min的时序修复时间,缩短了芯片的设计周期。Fixing timing in customized processors design is always a difficult task.In order to meet all timing requirements of WS_CPU with 14nm process,this paper proposes an efficient and reliable design methodology:(1)the new FCHT(Flexible Configurable H-Tree)implement even clock signal allocation and reduce routing time.Meanwhile,adopting the CCOPT(Clock Concurrent Optimization)technology to optimize the clock tree;(2)DCG(Design Compiler Graphical)mode and ICG(Integrate Clock Gating)technology are used in the synthesis phase to assess design risks to reduce the design iterative time of layout and routing.With this methodology,the setup time of WS_CPU can achieve to 108 ps at 1 GHz working frequency.Moreover,compared with the traditional balanced tree,flexible H-Tree and 3-level H-Tree,the total power of the chip in FCHT structure is reduced by 7.71%,6.18%and 7.87%.And it outperforms the traditional balanced tree by saving 3156 min,the Flexible H-Tree by saving 5200 minutes,shortening the design cycle of the chip.

关 键 词：时序收敛 设计周期 FCHT时钟结构 柔性H树 时钟树综合 

分 类 号：TN492[电子电信—微电子学与固体电子学] TN402