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作 者:王俊 徐辉[1] WANG Jun;XU Hui(School of Computer and Engineering,Anhui University of Science and Technology,Huainan 232001,China)
机构地区:[1]安徽理工大学计算机科学与工程学院,安徽淮南232001
出 处:《华北科技学院学报》2024年第2期54-62,84,共10页Journal of North China Institute of Science and Technology
基 金:国家自然科学基金面上项目(61404001)。
摘 要:随着CMOS集成电路工作频率和工艺的提升,深纳米级电路在高辐射空间环境中也越来越容易受到辐射粒子撞击引起的软错误影响。本文提出了一种低成本的quadruple-node-upsets(QNUs)容忍锁存器设计LCQNUTL,由三个独立的存储单元SC和拦截模块CG-SIM组成。SC内部两个二元反相器DI进行反馈互锁组成一个环路,通过Dual-inverter(DI)的特性达到实现SC单元可以单节点翻转的自恢复能力;再通过CG-SIM将存储单元SC中的部分错误节点进行过滤,所提出的LCQNUTL锁存器可以完全容忍QNU。仿真结果也验证了LCQNUTL锁存器的鲁棒性。与目前相同类型的QNU容忍锁存器设计相比,功耗平均降低53.21%,延迟平均降低53.83%,PDP平均降低77.27%。With the increase in working frequency and technology of CMOS integrated circuits,deep sub-nanometer circuits are becoming more susceptible to soft errors caused by radiation particle impacts in high radiation space environments.This paper proposes a low-cost quadruple-node-upsets(QNUs)tolerant latch design,LCQNUTL,which consists of three independent storage units(SC)and an interception module(CG-SIM).Two binary inverters(DI)inside the SC form a feedback interlock loop,which achieves the self-recovery capability of single-node flipping in the SC unit by the characteristics of the Dual-inverter(DI).Then,a portion of the error nodes in the storage unit SC is filtered through the CG-SIM.The proposed LCQNUTL latch can completely tolerate QNU.The simulation results also verify the robustness of the LCQNUTL latch.Compared with current QNU-tolerant latch designs of the same type,the power consumption is reduced by an average of 53.21%,the delay is reduced by an average of 53.83%,PDP is reduced by an average of 77.27%.
分 类 号:TN47[电子电信—微电子学与固体电子学]
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