DVB-T中伪随机序列扰码器的FPGA实现  

FPGA Implementation of Pseudo-random Sequence Scrambler in DVB-T

作　　者：陈振林 CHEN Zhenlin(Electronic Information School,Foshan Polytechnic,Foshan 528137,China)

机构地区：[1]佛山职业技术学院电子信息学院,广东佛山528137

出　　处：《现代信息科技》2024年第7期11-14,18,共5页Modern Information Technology

摘　　要：伪随机序列在伪码测距、导航、数字数据扰乱器、噪声产生器、通信加密中有着广泛的应用。在这些实际应用中,常常利用现场可编程门阵列(FPGA)来产生伪随机序列,这便于系统设计和测试的实现。针对数字地面电视广播(DVB-T)标准,以线性反馈移位寄存器电路为基础,设计了一种并行伪随机序列产生方法,该方法简单而高效地实现DVB-T系统码流数据的扰码。实验结果表明,MATLAB扰码算法结果与FPGA扰码模块仿真结果和硬件实现结果一致,该设计方法切实可行。Pseudo-random sequence is widely used in pseudo-code ranging,navigation,digital data scramblers,noise generators and communication encryption.In the practical application,the FPGA is usually used to generate pseudo-random sequences,which can bring great convenience to system design or testing.Aiming at the DVB-T standard,based on the linear feedback shift register circuit,a simple and efficient parallel pseudo-random sequence generation method is designed to realize the scrambling of DVB-T system code flow data.The experimental results show that the MATLAB scrambling algorithm results are consistent with the FPGA scrambling module simulation results and hardware implementation results,so the design method is feasible.

关 键 词：伪随机序列 DVB-T MATLAB FPGA VERILOG 

分 类 号：TN914.3[电子电信—通信与信息系统]