应用于0.5~12.5Gb/s CMOS时钟数据恢复电路的相位插值器设计  

Design of phase interpolator for 0.5~12.5 Gb/s CMOS clock data recovery circuit

作　　者：张媛菲 赵宏亮[1] 尹飞飞[1] ZHANG Yuanfei;ZHAO Hongliang;YIN Feifei(School of Physics,Liaoning University,Shenyang 110036,China)

机构地区：[1]辽宁大学物理学院,辽宁沈阳110036

出　　处：《电子设计工程》2024年第10期130-134,共5页Electronic Design Engineering

基　　金：辽宁省自然科学基金项目(2021-MS-148)。

摘　　要：文中采用28 nm CMOS工艺,设计了一款应用于半速率CDR电路中的相位插值器。该插值器采用锁相环提供的正交参考时钟,通过编码控制的DAC电流源调整电流权重控制输出相位,一个周期内可实现128次相位插值。为了提高接收器在多通道、多协议的性能,提出了输入时钟整形电路对斜率进行调节,提高了线性度。仿真结果表明,插值器在6.25 GHz工作频率下线性度良好,微分非线性(DNL)最大不超过1 LSB,积分非线性(INL)最大不超过2 LSB,实现了高线性度、宽频率范围的设计目标。This paper presents a phase interpolator is designed for half⁃rate CDR circuits using 28 nm CMOS technology.The interpolator uses the orthogonal reference clock provided by the phase⁃locked loop.The output phase is controlled by the current weight adjusted by the code controlled by the current source of the DAC,and 128 phase interpolants can be achieved in one cycle.In order to improve the receiver’s performance in multi⁃channel and multi⁃protocol,an input clock shaping circuit is proposed to adjust the slope and improve the linearity.The simulation results show that the interpolator has good linearity at the operating frequency of 6.25 GHz,and the maximum Differential Non⁃Linearity(DNL)is less than 1 LSB,and the maximum Integral Non⁃Linearity(INL)is less than 2 LSB.It achieves the design goal of high linearity and wide frequency range.

关 键 词：相位插值器 线性度 时钟恢复电路 半速率 正交时钟 

分 类 号：TN432[电子电信—微电子学与固体电子学]