基于CNFET电路段内关键门的全局布局算法  

Global Layout Algorithm Based on Key Gates within Segments of CNFET Circuits

作　　者：田康林 赵康[2] Tian Kanglin;Zhao Kang(School of Science,Beijing University of Posts and Telecommunications,Beijing 100876;School of Integrated Circuits,Beijing University of Posts and Telecommunications,Beijing 100876)

机构地区：[1]北京邮电大学理学院,北京100876 [2]北京邮电大学集成电路学院,北京100876

出　　处：《计算机辅助设计与图形学学报》2024年第3期464-472,共9页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家重点研发计划资助(2022YFB2901100)。

摘　　要：针对传统硅基电路布局算法在碳纳米管(CNT)密度变化的碳纳米管场效应晶体管(CNFET)电路上表现出时序良率不高的问题,提出一种基于段内关键门的全局布局算法.首先自底向上逐级分析电路各个层级,依次建立门延迟、门树延迟模型,在此基础上结合CNFET电路相关矩阵建立包含延迟均值和方差的段统计延迟模型;然后通过理论分析确定时序良率与段的统计延迟之间的相关关系;最后利用CNFET电路不对称空间相关性,使用网格搜索策略不断迭代调整段内关键门位置,以降低段延迟.在OpenCores中4个测试电路上的实验结果表明,所提算法平均提高了20%的电路时序良率,在执行时间上比CNT密度变化感知的基准方法降低25%,揭示了其在高时序良率要求的大规模电路中应用的潜力.Aiming at the problem that traditional silicon-based circuit layout algorithms show low timing yields on carbon nanotube field effect transistor(CNFET)circuits with varying carbon nanotube(CNT)densities,a global layout algorithm based on the key gates in a segment is proposed.Firstly,we analyze each level of the circuit from the bottom to the top,and establish the gate delay and gate tree delay models,and then we combine the CNFET circuit correlation matrix to establish the statistical delay model of the segment with the mean and variance of the delay;then,we determine the correlation between the timing yield and the statistical delay of the segment through the theoretical analysis;finally,we use the asymmetric spatial correla-tion of CNFET circuits,and we use the lattice search strategy to continuously adjust the key gates in the seg-ment by iteration.Finally,using the asymmetric spatial correlation of CNFET circuits,a grid search strategy is used to iteratively adjust the positions of key gates in the segment to reduce the segment delay.Experimental results on four OpenCores test circuits show that the proposed algorithm improves the circuit timing yield by 20%on average,and reduces the execution time by 25%compared with the CNT density-aware benchmark method,which reveals its potential application in large-scale circuits with high timing yield requirements.

关 键 词：碳纳米管 碳纳米管场效应晶体管 不对称空间相关性 全局布局算法 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术]