高性能自研处理器物理设计频率提升方法  

Promoting Frequency Method for Our Own High Performance Processor Physical Design

作　　者：何小威[1,2] 乐大珩 郭维[1,2] 隋兵才 邓全[1,2] He Xiaowei;Yue Daheng;Guo Wei;Sui Bingcai;Deng Quan(College of Computer Science and Technology,National University of Defense Technology,Changsha 410073;Key Laboratory of Advanced Microprocessor Chips and Systems(National University of Defense Technology),Changsha 410073)

机构地区：[1]国防科技大学计算机学院,长沙410073 [2]先进微处理器芯片与系统重点实验室(国防科技大学),长沙410073

出　　处：《计算机研究与发展》2024年第6期1429-1435,共7页Journal of Computer Research and Development

基　　金：国防科技大学科研计划项目(ZK22-05);全军共用信息系统装备预研专用技术项目(31513010105)。

摘　　要：提升处理器核的频率是提升处理器性能的重要手段.传统的物理设计流程难以实现高主频的处理器核.基于业界主流的布局布线工具,通过嵌入手工定制部件的网表、逻辑和物理设计协同优化、优化定制布线规则、优化物理设计方法学等组合策略.在相同工艺、面积、功耗对等条件下,达到流片签核要求时,自研处理器核物理设计频率比原始设计可提升约30%.Promoting core’s frequency is the key method for increasing performance of processor.It is hard to achieve high frequency for processor core by traditional physical design flow.Based on main place and route tools,with the same process,comparable implementation area and power consumption,our own processor core frequency can be pro-moted by about 30%compared with original design at signoff stage,by employing manually written block netlist,logic and physical design co-optimization,custom routing rule optimization and physical design methodology adjustment.

关 键 词：布局布线 协同优化 物理设计 签核 频率 

分 类 号：TN47[电子电信—微电子学与固体电子学]