基于DDS+PLL的频率合成方法研究  

Research on Frequency Synthesis Method Based on DDS+PLL

作　　者：王锋 郭中会 庞洋 张一萌 陈鹏 WANG Feng;GUO Zhong-hui;PANG Yang;ZHANG Yi-meng;CHEN Peng(Tianjin 712 Communication&Broadcasting Co.,Ltd.,Tianjin 300462)

机构地区：[1]天津七一二通信广播股份有限公司,天津300462

出　　处：《环境技术》2024年第4期155-159,共5页Environmental Technology

摘　　要：针对传统的PLL在小数分频时引起的边界杂散问题,采用DDS作为PLL的参考时钟,通过动态调整DDS的输出频率及PLL的整数分频比,使PLL在整数分频模式下仍具有小步进的合成频率精度。经过理论分析和实测实验验证了方案的可行性,实测实验表明,采用DDS+PLL方案合成频率可以有效解决整数边界杂散,并实现了最大9.31 Hz的频率步进精度。In response to the boundary spurious problem caused by traditional PLL during fractional division,DDS is used as the reference clock of PLL.By dynamically adjusting the output frequency of DDS and the integer division ratio of PLL,PLL still has small step synthesis frequency accuracy in integer division mode.The feasibility of the scheme has been verified through theoretical analysis and practical experiments.The practical experiments have shown that using DDS+PLL scheme to synthesize frequency can effectively solve integer boundary noise and achieve a maximum frequency stepping accuracy of 9.31 Hz.

关 键 词：小数分频 边界杂散 DDS激励PLL 小步进 频率精度 

分 类 号：TN99[电子电信—信号与信息处理] TN92[电子电信—信息与通信工程]